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Adaptive Circuit Technique for Managing Power Consumption

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Adaptive Techniques for Dynamic Processor Optimization

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References

  1. T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama, “Variable supply-voltage scheme for low-power high-speed CMOS digital design,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 454–462, Mar. 1998.

    Article  Google Scholar 

  2. T. Sakurai, “Low power digital circuit design (keynote),” ESSCIRC'04, pp. 11–18, Sept. 2004. T. Sakurai, “Perspectives of low-power VLSI's,” IEICE Transactions on Electronics, vol. E87-C, no. 4, pp. 429–437, Apr. 2004.

    Google Scholar 

  3. A. Chandrakasan, V. Gutnik, and T. Xanthopoulos, “Data driven signal processing: an approach for energy efficient computing,” Proc. ISLPED’ 96, pp. 347–352, Aug. 1996.

    Google Scholar 

  4. K. Aisaka, T. Aritsuka, S. Misaka, K. Toyama, K. Uchiyam, K. Ishibashi, H. Kawaguchi, and T. Sakurai, “Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder,” Symp. on VLSI Circuits Digest of Technical Papers, pp. 216–217, Jun. 2002.

    Google Scholar 

  5. T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, “A 0.9 V 150 MHz 10mW 4 mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1770–1779, Nov. 1996.

    Article  Google Scholar 

  6. T. Sakurai and A. R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584–594, Apr. 1990.

    Article  Google Scholar 

  7. T. Kobayashi and T. Sakurai, “Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation,” Proc. CICC’94, pp. 271–274, May 1994.

    Google Scholar 

  8. K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, “50% active-power saving without speed degradation using standby power reduction (SPR) circuit,” ISSCC Dig. Tech. Papers, pp. 318–319, Feb. 1995.

    Google Scholar 

  9. T. Kuroda, T. Fujita, T. Nagamatu, S. Yoshioka, T. Sei, K. Matsuo, Y. Hamura, T. Mori, M. Murota, M. Kakumu, and T. Sakurai, “A high-speed low-power 0.3 μm CMOS gate array with variable threshold voltage (VT) scheme,” Proc. CICC’96, pp. 53–56, May 1996.

    Google Scholar 

  10. T. Kuroda, T. Fujita, S. Mita, T. Mori, K. Matsuo, M. Kakumu, and T. Sakurai, “Substrate noise influence on circuit performance in variable threshold-voltage scheme,” Proc. ISLPED’96, pp. 309–312, Aug. 1996.

    Google Scholar 

  11. T. Kuroda and T. Sakurai, “Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design,” J. VLSI Signal Processing Systems, Kluwer Academic Publishers, vol. 13, no. 2/3, pp. 191–201, Aug./Sep. 1996.

    Google Scholar 

  12. R. D. Pashley and G. A. McCormick, “A 70-ns 1 K MOS RAM,” ISSCC Dig. Tech. Papers, pp. 138–139, Feb. 1976.

    Google Scholar 

  13. M. Takahashi, M. Hamada, T. Nishikawa, H. Arakida, Y. Tsuboi, T. Fujita, F. Hatori, S. Mita, K. Suzuki, A. Chiba, T. Terasawa, F. Sano, Y. Watanabe, H. Momose, K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, T. Kuroda, and T. Furuyama, “A 60mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme,” ISSCC Dig. Tech. Papers, pp. 34–35, Feb. 1998.

    Google Scholar 

  14. K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, “Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSI’s,” Proc. CICC’99, pp. 563–566, May 1999.

    Google Scholar 

  15. A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, and V. De, “Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs,” Proc. LPED’01, pp. 207–212, Aug. 2001.

    Google Scholar 

  16. M. Togo, T. Fukai, Y. Nakahara, S. Koyama, M. Makabe, E. Hasegawa, M. Nagase, T. Matsuda, K. Sakamoto, S. Fujiwara, Y. Goto, T. Yamamoto, T. Mogami, M. Ikeda, Y. Yamagata, and K. Imai, “Power-aware 65 nm node CMOS technology using variable VDD and back-bias control with reliability consideration for back-bias mode,” Symp. on VLSI Technology Dig. Tech. Papers, pp. 88–89, June 2004.

    Google Scholar 

  17. S. Narendra, M. Haycock, V. Govindarajulu, V. Erraguntla, H. Wilson, S. Vangal, A. Pangal, E. Seligman, R. Nair, A. Keshavarzi, B. Bloechel, G. Dermer, R. Mooney, N. Borkar, S. Borkar, and V. De, “1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS,” ISSCC Dig. Tech. Papers, pp. 270–271, Feb. 2002.

    Google Scholar 

  18. S. Vangal, M. A. Anders, N. Borkar, E. Seligman, V. Govindarajulu, V. Erraguntla, H. Wilson, A. Pangal, V. Veeramachaneni, J. Tschanz, Y. Ye, D. Somasekhar, B. Bloechel, G. Dermer, R. K. Krishnamurthy, K. Soumyanath, S. Mathew, S. Narendra, M. Stan, S. Thompson, V. De, and S. Borkar, “5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1421–1432, Nov. 2002.

    Article  Google Scholar 

  19. S. Narendra, A. Keshavarzi, B. A. Bloechel, S. Borkar, and V. De, “Forward body bias for microprocessors in 130-nm technology generation and beyond,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 696–701, May 2003.

    Article  Google Scholar 

  20. M. Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama, and K. Ishibashi, “A 1000-MIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias,” ISSCC Dig. Tech. Papers, pp. 420–421, Feb. 2000.

    Google Scholar 

  21. G. Ono and M. Miyazaki, “Threshold-voltage balance for minimum supply operation,” Symp. VLSI Circuits Dig. 16, pp. 206–209, June 2002.

    Google Scholar 

  22. J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antonladls, A. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of doe-to-deiand within-die parameter variations on microprocessor frequency and leakage,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1396–1402, Nov. 2002.

    Article  Google Scholar 

  23. K. Ishibashi, T. Yamashita, Y. Arima, I. Minematsu, and T. Fujimoto, “A 9μW 50 MHz 32b adder using a self-adjusted forward body bias in SoCs,” ISSCC Dig. Tech. Papers, pp. 116–117, Feb. 2003.

    Google Scholar 

  24. Q. Liu, T. Sakurai, and T. Hiramoto, “Optimum device consideration for standby power reduction scheme using drain-induced barrier lowering,” Jpn. J. Apply. Phys. vol. 42, no. 4B, pp. 2171–2175, Apr. 2003.

    Article  Google Scholar 

  25. T. Kuroda, “Optimization and control of VDD and VTH for low-power, high-speed CMOS design (invited),” ICCAD’02 Dig. Tech. Papers, pp. 28–34, Nov. 2002.

    Google Scholar 

  26. S. Lee and T. Sakurai, “Run-time voltage hopping for low-power real-time systems,” Proc. DAC’00, pp. 806–809, June 2000.

    Google Scholar 

  27. Y. Shin, H. Kawaguchi, and T. Sakurai, “Cooperative Voltage Scaling (CVS) between OS and applications for low-power real-time systems,” Proc. CICC’01, pp. 553–556, May 2001.

    Google Scholar 

  28. H. Kawaguchi, Y. Shin, and T. Sakurai, “μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications,” IEEE Transaction on Multimedia, vol. 7, no. 1, pp. 67–74, Feb. 2005.

    Article  Google Scholar 

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Kuroda, T., Sakurai, T. (2008). Adaptive Circuit Technique for Managing Power Consumption. In: Wang, A., Naffziger, S. (eds) Adaptive Techniques for Dynamic Processor Optimization. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-76472-6_3

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  • DOI: https://doi.org/10.1007/978-0-387-76472-6_3

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