Although complementary metal-oxide semiconductor (CMOS) chips are projected to continue their dominance for another 10—15 years [1], CMOS technology today faces a number of challenges. Quantum effects will soon make it nearly impossible to further scale devices. Deep sub-micron (DSM) technologies suffer from high leakage, and it is projected that stand-by power and active power for CMOS chips will soon become comparable [2]. Moreover, the high cost associated with chip masks and next-generation fabrication plants poses a formidable economic barrier to commercial nanometer-scale lithography.
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Wang, Z., Chakrabarty, K. (2008). Built-in Self-Test and Defect Tolerance in Molecular Electronics-Based Nanofabrics. In: Tehranipoor, M. (eds) Emerging Nanotechnologies. Frontiers in Electronic Testing, vol 37. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-74747-7_2
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