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Placement for Power Optimization

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Closing the Power Gap Between ASIC & Custom

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Circuit placement is a well studied area of VLSI design. The logic elements in a circuit design must be transferred onto the silicon substrate – transistors are not allowed to overlap, and there are a variety of spacing and size constraints. In this chapter, we survey techniques to minimize power within a placement context. By “placement”, we mean a mapping of each logic element to a physical location.

Minimization of power during circuit placement requires a delicate balance of constraints. There is always a trade-off between power and speed. If speed is not an issue, power can be reduced by operating at a low frequency, increasing device threshold voltages, and down-sizing devices which reduces the layout area. However for modern circuits, it’s rare to have such low performance objectives. Rather, the challenge is to design a circuit that is both fast and low power.

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Authors and Affiliations

  1. Computer Science Department T. J. Watson School of Engineering, State University of New York, 6000, 13902, Binghamton, NY, USA

    Ameya R. Agnihotri, Satoshi Ono & Patrick H. Madden

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  1. Ameya R. Agnihotri
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  2. Satoshi Ono
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  3. Patrick H. Madden
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Agnihotri, A.R., Ono, S., Madden, P.H. (2007). Placement for Power Optimization. In: Closing the Power Gap Between ASIC & Custom. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68953-1_9

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  • DOI: https://doi.org/10.1007/978-0-387-68953-1_9

  • Publisher Name: Springer, Boston, MA

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  • Online ISBN: 978-0-387-68953-1

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