This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Reference
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, NY, 2001.
S. Rusu, S. Tam, H. Muljono, D. Ayers, and J. Chang, “A dual-core multi-threaded Xeon processor with 16 MB L3 cache,” ISSCC Dig. Tech. Papers, pp. 102–103, Feb. 2006.
Y. Nakagome, M. Horiguchi, T. Kawahara, K. Itoh, “Review and prospects of low-voltage RAM circuits,” IBM J. R & D, vol. 47, no. 5/6, pp. 525–552, Sep./Nov. 2003.
M.I.Elmasry, Ed., Digital MOS Integrated Circuits 2 (IEEE Press, New York 1992).
E. Hamdy and A. Mohsen, “Characterization and modeling of transient latch-up in CMOS technology,” IEDM Dig. Tech. Papers, pp.172–173, 1983.
J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, et al., “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” IEDM Dig. Tech. Papers, pp. 247–250, Dec. 2004.
International Technology Roadmap for Semiconductors, 2004 Update, Emerging Research Devices, pp. 9–14.
T.C. Chen, “Where CMOS is going: Trendy Hype vs. Real Technology,” ISSCC Dig. Tech. Papers, pp. 22–28, Feb. 2006.
K. Nii, Y. Tenoh, T. Yoshizawa, S. Imaoka, Y. Tsukamoto, Y. Yamagami, T. Suzuki, A. Shibayama, H. Makino, and S. Iwade, “A 90-nm low-power 32K-Byte embedded SRAM with gate leakage suppression circuit for mobile applications,” Symp. VLSI Circuits Dig., pp. 247–150, June 2003.
T. Inukai et al., “Suppression of stand-by tunnel current in ultra-thin gate oxide MOSFETs by dual oxide thickness MTCMOS,” Int. Conf. on Solid-State Dev. and Mat. Ext. Abst., pp. 264–265, Aug. 1999.
K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi,“16.7fA/cell tunnel-leakage-suppressed 16-Mbit SRAM based on electric-field-relaxed scheme and alternate ECC for handling cosmic-ray-induced multi-errors,” ISSCC Dig. Tech Papers, pp. 302–303, Feb. 2003.
D. J. Frank, “Power-constrained CMOS scaling limits,” IBM J. Res. & Dev., vol. 46, pp. 235–244, Mar. 2002.
G. Ono, M. Miyazaki, H. Tanaka, N. Ohkubo, and T. Kawahara, “Temperature referenced supply voltage and forward-body-bias controled (TSFC) architecture for minimum power consumption,” ESSCIRC Dig. Tech. Papers, pp. 391–394, 2004.
S. Heo and K. Asanovic, “Leakage-biased domino circuits for dynamic fine-grain leakage reduction,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 316–319, June 2002.
H. Yoon, J. Y. Sim, H. S. Lee, K. Nam Lim et al., “A 4Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture,” ISSCC Dig. Tech. Papers, pp. 378–379, Feb. 2001.
S. Naffziger, B. Stackhouse, and T. Grutkowski, “The implementation of a 2-core multi-threaded Itanium®-family processor,” ISSCC Dig. Tech. Papers, pp. 182–183, Feb. 2005.
Y. H. Suh, H. Y. Nam, S. B. Kang, B. G. Choi, H. S. Mo, G. H. Han, H. K. Shin, W. R. Jung, H. Lim, C. K. Kwak, H. G. Byun, “A 256 Mb synchronous-burst DDR SRAM with hierarchical bit-line architecture for mobile applications,” ISSCC Dig. Tech. Papers, pp. 476–477, Feb. 2005.
D-S Byeon, S-S Lee, Y-H Lim, J-S Park et al., “An 8Gb multi-level NAND Flash memory with 63nm STI CMOS process technology,” ISSCC Dig. Tech. Papers, pp. 46–47, Feb. 2005.
K. Takeuchi, Y. Kameda, S. Fujimura, H. Otake et al., “A 56nm CMOS 99mm2 8Gb multi-level NAND Flash memory with 10 MB/s program throughput,” ISSCC Dig. Tech. Papers, pp. 144–145, Feb. 2006.
F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, and S. Tanaka, “A new Flash EEPROM cell using triple polysilicon technology,” IEDM Dig. Tech. Papers, pp. 464–467, Dec. 1984.
P. Pavin, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview,” IEEE Proc. Vol. 85, No.8, 1248–1271, 1997.
V. N. Kynett, A. Baker, M. Fandrich, G. Hoekstra, O. Jungroth, J. Kreifels, and S. Wells, “An in-system reprogrammable 256K CMOS Flash memory,” ISSCC Dig. Tech. Papers, pp. 132–133, Feb. 1988.
S. Haddad, C. Chang, A. Wang, J. Bustillio, J. Lien, T. Montalvo, and M.V. Buskirk, “An investigation of erase-mode dependent hole trapping in Flash EEPROM memory cell,” Electron Device Letters, vol. 11, no.11, pp. 514–516, Nov. 1990.
F. Masuoka, M. Momodori, Y. Iwata, and R. Shirota, “New ultra high density EPROM and Flash EEPROM cell with NAND structure cell,” IEDM Dig. Tech. Papers, pp. 552–555, 1987.
T. Hara, K. Fukuda, K. Kanazawa, N. Shibata, et al., “A 146-mm2 8-Gb multi-level NAND Falsh memory with 70-nm CMOS technology,” IEEE J. Solid-Sate Circuits, Vol. 41, No. 1, pp.161–169, Jan. 2006.
K. Imamiya, Y. Sugiura, H. Nakamura, T. Himeno, K. Takeuchi, T, Ikehashi, K. Kanda, K. Hosono, R. Shirota, S. Aritomo, K. Shimizu, K. Hatakeyama, and K. Sakui, “A 130-mm2, 256-Mb NAND Flash with shallow trench isolation technology,” IEEE J. Solid-State Circuits, Vol.34, No.11, pp. 1536–1543, Nov. 1999.
T. Tanzawa and S. Atsumi, “Optimization of word-line booster circuits for low-voltage Flash memories,” IEEE J. Solid-State Circuits, Vol.34, No.8, pp. 1091–1098, Aug. 1999.
T. Tanzawa, T. Tanaka, K. Takeuchi, and H. Nakamura, “Circuit techniques for a 1.8-V-only NAND Flash memory,” IEEE J. Solid-State Circuits, Vol.37, No.1, pp. 84–89, Jan. 2002.
J.F. Ziegler, H. W. Curtis, H. P. Muhlfeld, C. J. Montrose, et al., “IBM experiments in soft fails in computer electronics (1978–1994),” IBM J. Res. Develop., vol.40, no.1. pp. 3–18, Jan. 1996.
K. Osada, K. Yamaguchi, Y. Saitoh, and T. Kawahara, “SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect,” IEEE J. Solid-State Circuits, vol. 39, No.5, pp. 827–833, May 2004.
Y. Komatsu, Y. Arima, T. Fujimoto, T. Yamashita, and K. Ishibashi, “A soft-error hardened latch sceme for SoC in a 90 nm technology and beyond,” CICC Dig. Tech. Papers, pp. 329–332, Oct. 2004.
T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, et al., “A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay,” IEEE J. Solid-State Circuits, vol. 31, no.11, pp. 1656–1668, Nov. 1996.
M. Kubo, R. Hori, O. Minato and K. Sato, “A threshold voltage controlling circuit for short channel MOS integrated circuits,” ISSCC Dig. Tech. Papers, pp. 54–55, Feb. 1976.
E. M. Blaser, W. M. Chu, and G. Sonoda, “Substrate and load gate voltage compensation,” ISSCC Dig. Tech. Papers, pp. 56–57, Feb. 1976.
T. Burd, T. Pering, A. Stratakos and R. Brodersen, “A dynamic voltage scaled microprocessor system,” ISSCC Dig. Tech. Papers, pp. 294–295, Feb. 2000.
K. Itoh, “Analog circuit techniques for RAMs-present and future-,” Analog VLSI Workshop, 2005 IEEJ, Dig. Tech. Papers, pp. 1–6, Bordeaux, Oct. 2005.
K. Itoh, K. Osada, and T. Kawahara, “Reviews and prospects of low-voltage embedded RAMs,” CICC Dig. Tech. Papers, pp. 339–344, Oct. 2004.
Phillip E. Allen and Douglas R. Holberg: “CMOS analog circuit design,” New York: Holt, Rinehart and Winston, INC.1987.
T. Mano, J. Yamada, J. Inoue and S. Nakajima, “Circuit techniques for a VLSI memory,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 463–469, Oct. 1983.
H. L. Kalter, C. H. Stapper, J. E. Barth Jr., J. DiLorenzo, C. E. Drake, J. A. Fifield, G. A. Kelley Jr., S. C. Lewis, W. B. van der Hoeven and J. A. Yankosky, “A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC,” IEEE J. Solid-State Circuits, vol. 25, pp. 1118–1128, Oct. 1990.
K. Arimoto, K. Fujishima, Y. Matsuda, M. Tsukude, T. Oishi, W. Wakamiya, S. Satoh, M. Yamada and T. Nakano, “A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register,” IEEE J. Solid-State Circuits, vol. 24, pp. 1184–1190, Oct. 1989.
F. Morishita, K. Suma, M. Hirose, T. Tsurude, Y. Yamaguchi, T. Eimori, T. Oashi, K. Arimoto, Y. Inoue, and T. Nishimura, “Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI DRAM,” Symp. VLSI Tech. Dig. Tech. Papers, pp. 141–142, 1995.
Low-power High-speed LSI Circuits & Technology, REALIZE INC., 1998 (in Japanese).
S. Satoh, Y. Tosaka, and T. Itakura, “Scaling law for secondary cosmic-ray neutron-induced soft-errors in DRAMs,” Ext. Abstract, Int’l Conf. Solid-State Devices and Materials, pp. 40–41,1998.
M. Hiraki, K. Fukui and T. Ito, “A low-power microcontroller having a 0.5-μA standby current on-chip regulator with dual-reference scheme,” IEEE J. Solid-State Circuits, vol. 39, pp. 661–666, Apr. 2004.
K. Itoh, VLSI Memory Design, Baifukan, Tokyo, 1994 (in Japanese).
M. Momodori, Y. Itoh, R. Shirota, Y. Iwata, R. Nakayama, R. Kirisawa, T. Tanaka, S. Aritome, T. Endoh, K. Ohuchi, and F. Masuoka, “An experimental 4-Mbit CMOS EEPROM with a NAND-structured Cell,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1238–1243, Oct. 1989.
M. Momodori, T. Tanaka, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R. Shirota, K. Ohuchi, and F. Masuoaka, “A 4-Mb NAND EEPROM with tight programmed Vt distribution,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 492–496, Apr. 1991.
H. Gotou, Y. Arimoto, M. Ozeki, and K. Imaoka, “Soft error rate of SOI-DRAM,” IEDM Dig. Tech. Papers, pp. 870–871, 1987.
K. Ishibashi, T. Yamashita, Y. Arima, I. Minematsu and T. Fujimoto, “A 9mW 50MHz 32b adder using a self-adjusted forward body bias in SoCs,” ISSCC Dig. Tech. Papers, p. 116–117, Feb. 2003.
Y. Komatsu, K. Ishibashi, M. Yamamoto, T. Tsukada, K. Shimazaki, M. Fukazawa, and M. Nagata, “Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias,” CICC Dig. Tech. Papers, pp. 35–38, 2005.
K. Ishibashi, T. Fujimoto, T. Yamashita, H. Okada, Y. Arima, Y. Hashimoto, K. Sakata, I. Minematsu, Y. Itoh, H. Toda, M. Ichihashi, Y. Komatsu, M. Hagiwara, and T. Tsukada, “Low-voltage and low-power logic, memory, and analog circuit techniques for SoCs using 90nm technology and beyond (invited),” IEICE Tran. on Electronics, Vol.E89-C, No.3, pp. 250–262, 2006.
Leakage in Nanometer CMOS Technologies, Edited by S. G. Narendra and A. Chandrakasan, Springer, 2006.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer Science+ Business Media, LLC
About this chapter
Cite this chapter
Itoh, K., Horiguchi, M., Tanaka, H. (2007). An Introduction to LSI Design. In: Itoh, K., Horiguchi, M., Tanaka, H. (eds) Ultra-Low Voltage Nano-Scale Memories. Series On Integrated Circuits And Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68853-4_1
Download citation
DOI: https://doi.org/10.1007/978-0-387-68853-4_1
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-33398-4
Online ISBN: 978-0-387-68853-4
eBook Packages: EngineeringEngineering (R0)