Abstract
We consider the problem of simulating a PRAM on a faulty distributed memory machine (DMM). We focus on dynamic faults, i.e. each processor or memory module independently fails during the simulation of a PRAM step with fixed probability and remains faulty for the rest of the simulation. We build upon randomized hashing-based simulations on non-faulty DMMs from [14], which achieve delay O (log log n), with high probability. We design and analyze routines for handling faults occurring during the simulation. Based on these routines we present simulations on faulty DMMs with the same delay O(log log n) as in the non-faulty case, provided that the failure probability of processors and modules is small enough to guarantee an expected linear number of processors and modules to survive the simulation. Thus the facility of being resilient to memory or processor faults increases the delay of the simulation at most by a constant factor.
Supported in part by DFG-Graduiertenkolleg “Parallele Rechnernetzwerke in der Produktionstechnik”, ME 872/4-1, by DFG-SFB 376 “Massive Parallelität, by the Esprit Basic Research Action Nr. 7141 (ALCOM II), and by the SICMA Project founded by the European Community within the program on “Advanced Communication Technologies and Services”.
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© 1996 Springer-Verlag Berlin Heidelberg
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Berenbrink, P., Meyer auf der Heide, F., Stemann, V. (1996). Fault-tolerant shared memory simulations. In: Puech, C., Reischuk, R. (eds) STACS 96. STACS 1996. Lecture Notes in Computer Science, vol 1046. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60922-9_16
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DOI: https://doi.org/10.1007/3-540-60922-9_16
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