Abstract
The proliferation of portable and hand-held electronics combined with increasing packaging costs is forcing circuit designers to adopt low power design methodologies. Low power designs of microprocessors and application specific integrated circuits (ASICs) result in increased battery life and improved reliability. In this paper, we examine the application of genetic algorithms to the low-power design of combinational logic. In particular, we consider the use of genetic algorithms for the optimization of standard cell based designs which account for 20–50% of a typical microprocessor die size. Our algorithm optimizes a user-specified function of delay, power, and area under performance constraints. Empirically, we find that the run time for our algorithm scales linearly with circuit size. In our extensive benchmark suite, this algorithm has reduced power by 17% on the average and as much as 24% on some circuits.
This research was supported in part by an NSF Graduate Fellowship and Joint Services Electronics Program (JSEP) under contract N00014-93-J-1270.
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© 1994 Springer-Verlag Berlin Heidelberg
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Hill, A.M., Kang, SM.(. (1994). Genetic algorithm based design optimization of CMOS VLSI circuits. In: Davidor, Y., Schwefel, HP., Männer, R. (eds) Parallel Problem Solving from Nature — PPSN III. PPSN 1994. Lecture Notes in Computer Science, vol 866. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58484-6_297
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DOI: https://doi.org/10.1007/3-540-58484-6_297
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