On the performance of networks with multiple busses

Abstract

We address the following questions:

• 1) To which extend can the computation power of parallel processor networks be increased by using busses, i.e. by providing broadcast facilities in the networks?

• 2) To which extend can shared memory cells of PRAMs be replaced by links? (For this question, note that a shared memory cell can be viewed as a global bus.)

We show upper and lower bounds for computing associative operations such as Addition or Maximum on networks with busses. Our bounds are based on simple graph theoretical properties of the networks.

As to question 1, these results demonstrate that busses can increase the performance of networks with large diameter. For example, computing MAXIMUM on a d-dimensional mesh with N processors needs time $\Theta (\sqrt[d]{N})$ without busses, but only time $\Theta \left( {\sqrt[{d + 1}]{{\tfrac{N}{m}}} + \log \log N} \right)$ with m CRCW-busses.

As to question 2, these results demonstrate that the storage requirement of optimal PRAM algorithms can be reduced by adding a network with small diameter. For example, an N-processor CRCW-PRAM with an underlying binary tree network needs $m \approx \frac{N}{{poly\log N}}$ (i.e. m with log m = log N - θ(log log N)) shared memory cells to compute Maximum in optimal time θ(log log N) whereas, without links, θ(N) shared memory cells are necessary.

We further consider a very simple, easy to realize class of networks with busses, namely planar networks with planar busses. We describe a planar system of EREW-busses for square meshes on which associative operations can be performed in optimal time θ(log N) — compared to θ(√N) without busses. On the other hand, we prove that Sorting on planar networks cannot be sped up by the use of additional planar busses.

Partially supported by DFG-Grants Me 872/1-4 and Di 412/2-1

Supported by DFG-Grant Me 872/1-4