Skip to main content

Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks

  • Conference paper
  • First Online:
Dependable Computing — EDCC-3 (EDCC 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1667))

Included in the following conference series:

Abstract

In this paper we consider path delay fault testing of a class of isomorphic Multistage Interconnection Networks (MINs) with centralized control using as representative the nxn Omega network. We show that the number of paths is 3n2-2n and we give a method for testing those applying only 2(3n-2) pairs of test vectors. We also show that this is the least number of test vector pairs that are required for testing all paths of the MIN. We also give a path selection method such that: a) the number of selected paths, that is, the number of paths that must be tested, is a small percentage of all paths and the propagation delay along every other path can be calculated from the propagation delays along the selected paths, b) all the selected paths are tested by using 2(3log2n+1) test vector pairs. Both methods derive strong delay—verification test sets.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. H. J. Siegel, Interconnection Networks for Large-Scale Parallel Processing, 2nd ed., New York: McGraw-Hill, 1990.

    Google Scholar 

  2. T. Feng, “A survey of Interconnection Networks”, Computer, pp. 12–27, December 1981.

    Google Scholar 

  3. D. P. Agrawal, “Testing and Fault Tolerance of Multistage Interconnection Networks”, Computer, pp. 41–53, April 1982.

    Google Scholar 

  4. V. P. Kumar and S. M. Reddy, “Augmented shuffle-exchange multistage interconnection networks”, Computer, pp. 30–40, June 1987.

    Google Scholar 

  5. Z. Brasilai and B. Rosen, “Comparison of ac self-testing procedures”, Proc. of ITC-83, pp. 560–571.

    Google Scholar 

  6. K. D. Wagner, “The error latency of delay faults in combinational and sequential circuits”, Proc. of ITC-85, pp. 334–341.

    Google Scholar 

  7. G. L. Smith, “Model for delay faults based upon paths”, Proc. of ITC-85, pp. 342–349.

    Google Scholar 

  8. J. D. Lesser and J. J. Shedletsky, “An Experimental Delay Test Generator for LSI Logic”, IEEE Trans. on Computers, vol. C-29 (3), pp. 235–248, March 1980.

    Article  Google Scholar 

  9. W. K. Lam, et al., “Delay fault coverage, test set size and performance trade-offs”, IEEE Trans. on CAD, vol. 14 (1), pp. 32–44, Jan. 1995.

    Google Scholar 

  10. S. Tani, et al., “Efficient Path Selection for Delay Testing Based on Partial Path Evaluation”, Proc. of 16th IEEE VLSI Test Symposium, pp. 188–193, 1998.

    Google Scholar 

  11. T. Haniotakis, Y. Tsiatouhas and D. Nikolos, “C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications”, 1998 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 155–163.

    Google Scholar 

  12. C. Wu and T. Feng, “On a Class of Multistage Interconnection Networks”, IEEE Transactions on Computers, vol. C-29 (8), pp. 694–702, August 1980.

    Article  MathSciNet  Google Scholar 

  13. M. A. Franklin, D.F. Wann and W.J. Thomas, “Pin Limitations and partitioning of VLSI Interconnection Networks”, IEEE Trans. on Computers, vol. C-31, pp. 1109–1116, November 1982.

    Article  Google Scholar 

  14. C. J. Lin and S. M. Reddy, “On Delay Fault Testing in Logic Circuits”, IEEE Trans. On CAD, pp. 694–703, September 1987.

    Google Scholar 

  15. K. Pramanick and S. M. Reddy, “On the Design of Path Delay Fault Testable Combinational Circuits”, Proc. of Fault Tolerant Computing, pp. 374–381, 1990.

    Google Scholar 

  16. J. Lin, S. M. Reddy and S. Patil, “An Automatic Test Pattern Generator for the Detection of Path Delay Faults”, Proc. of Int’l Conf. on CAD, pp. 284–287, 1987.

    Google Scholar 

  17. W. Ke and P. R. Menon, “Synthesis of Delay-Verifiable Combinational Circuits”, IEEE Trans. on Computers, pp. 213–222, Feb. 1995.

    Google Scholar 

  18. H. S. Stone, “Parallel Processing with the perfect shuffle”, IEEE Trans. on Computers, vol.C-20, pp. 153–161, 1971.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1999 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Bellos, M., Nikolos, D., Vergos, H.T. (1999). Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. In: Hlavička, J., Maehle, E., Pataricza, A. (eds) Dependable Computing — EDCC-3. EDCC 1999. Lecture Notes in Computer Science, vol 1667. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48254-7_19

Download citation

  • DOI: https://doi.org/10.1007/3-540-48254-7_19

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-66483-3

  • Online ISBN: 978-3-540-48254-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics