Abstract
This paper describes a successful hardware implementation of the RSA algorithm. It is implemented as an 120-bit bit-slice processor, which may be interconnected without additional circuitry to obtain arbitrary word lengths. With 512-bit operands, exponentiation takes less than 30 milliseconds.
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Keywords
- Application Specific Integrate Circuit
- Data Encryption Standard
- Modulo Reduction
- Additional Circuitry
- Security Processor
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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© 1988 Springer-Verlag Berlin Heidelberg
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Hoornaert, F., Decroos, M., Vandewalle, J., Govaerts, R. (1988). Fast RSA-Hardware: Dream or Reality?. In: Barstow, D., et al. Advances in Cryptology — EUROCRYPT ’88. EUROCRYPT 1988. Lecture Notes in Computer Science, vol 330. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45961-8_23
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DOI: https://doi.org/10.1007/3-540-45961-8_23
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