6. Conclusion and Outlook

Abstract

By now, technology development in IC test has a focus on off-line test. The test process after chip - respective wafer production is more and more intolerable from the financial and time point of view. In recent time, a trend is recognizably: the partial or full migration of test technology from off-chip to on-chip. The intention is to decrease of test time and costs by a combination of on-chip and external test (particularly for SOCs). Due to improved technologies, more silicon real estate becomes less a cost problem. It could and it is used for additional test facilities (e.g. test for embedded RAM). This offers also new possibilities for on-line testing or concurrent checking. The demand for on-line techniques exists partially in today’s integrated systems - especially with a safety critical relevance. For future systems with ‘nano-technology’, voltage levels below 1V, and clock-frequencies of several GHz, the necessity will arise for on-line check and also for fast error handling techniques. The reason will be the large part of errors caused by (today for the most part unimportant) transient effects, which cannot be handled anymore with reasonable costs.