Inversion/Division Systolic Architecture for Public-Key Cryptosystems in GF(2^m)

Abstract

Finite field arithmetic operations have been widely used in the areas of network security and data communication applications, and high-speed and low-complexity design for finite field arithmetic is very necessary for these applications. The current paper presents a new AB ² algorithm along with its systolic implementations in GF(2^m). The proposed algorithm is based on the MSB-first scheme using the standard basis representation. In addition, parallel-in parallel-out systolic architectures are also introduced using this algorithm as a foundation. The proposed architectures have a low hardware complexity and small latency compared to conventional architectures. In particular, the hardware complexity of AB ² and inversion/division array are about 25% lower than Wang's over GF(2^m), while the latency of AB ² and inversion/ division array are about 40% and 49.6% lower, respectively. Furthermore, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can also be utilized as the basic architecture for a crypto-processor.