Skip to main content

The MOSFET Transistor and the Memory Cell

  • Chapter
VLSI-Design of Non-Volatile Memories
  • 1482 Accesses

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 189.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 249.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 249.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Bibliography

  • S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Masoka, “Reliability issues of Flash memory cells,” Proc. IEEE, vol. 81, no. 5, pp. 776–788, (May 1993).

    Article  Google Scholar 

  • R. Bez et al., “Depletion Mechanism of Flash cell induced by parasitic drain stress contidion”, VLSI Technology Symposium, (1994).

    Google Scholar 

  • J. D. Bude, “Gate current by impact ionization feedback in sub-micron MOSFET technologies”, in 1995 Symposium VLSI Technology Dig. Tech. Pap., pp. 101–102, (June 1995).

    Google Scholar 

  • J. D. Bude, M.R. Pinto and R. K. Smith, “Monte Carlo Simulation of the CHISEL Flash Memory Cell,” IEEE Tran. Electron Devices, vol. 47, pp. 1873–1881, (Oct. 2000).

    Google Scholar 

  • E. Burstein, S. Lundqvist, “Tunneling Phenomena in Solida”, Plenum Press, New-York, (1969).

    Google Scholar 

  • E. Camerlenghi, P. Caprara, and G. Crisenza: “A 18 µm2 cell for megabit CMOS EPROM”, in Proc. 17th European Solid State Device Research Conf., pp. 765–768, (Sept. 1987).

    Google Scholar 

  • John Y. Chen, CMOS devices and technology for VLSI, Prentice Hall, (1990).

    Google Scholar 

  • A. Chimenton, P. Pellati, and P. Olivo, “Constant Charge Erasing Scheme for Flash Memories,” IEEE Tran. Electron Devices, vol. 49, pp. 613–618, (Apr. 2002).

    Google Scholar 

  • A. Chimenton, et al., “Overerase Phenomena: An insight Into Flash Memory reliability”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 617–626, (April 2003).

    Google Scholar 

  • C. Dunn, C. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Hefley, M. Middendorf, and T. San, “Flash EEPROM disturb mechanisms,” in Proc. Int. Rel. Phys. Symp., pp. 299–308, (April 1994).

    Google Scholar 

  • B. Eitan and D. Frohman-Bentchkowski, “Hot electron injection into the oxide in n-channel MOS devices”, IEEE Trans. Electron Devices, vol. ED-28, pp. 328–340, (March 1981).

    Google Scholar 

  • B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, and A. Modelli, “Multilevel Flash cells and their trade-offs”, in 1996 IEDM Tech. Dig., pp. 169–172, (Dec. 1996).

    Google Scholar 

  • Leo Esaki, “Long Journey into Tunneling”, Proceedings of IEEE, vol 62, No 6, pp 825–835, (June 1974).

    Google Scholar 

  • D. Frohman-Bentchkowsi, “Memory behavior in a floating gate avalanche-injection MOS (FAMOS) structure”, Appl. Phys. Lett., vol. 18, pp. 332–334, (1971).

    Google Scholar 

  • D. Frohman-Bentchkowsi, “FAMOS-A new semiconductor charge storage device”, Solid State Electron, vol. 17, pp. 517–520, (1974).

    Google Scholar 

  • C. Hu, “Lucky-electron model for channel hot-electron emission”, 1979 IEDM Tech. Dig., pp. 22–25, (Dec. 1979).

    Google Scholar 

  • C. Hu, “Future CMOS scaling and reliability”, Proc. IEEE, vol. 81, pp. 682–689, (May 1993).

    Article  Google Scholar 

  • Y. Igura et al., “New Device Degradation Due to "Cold" Carriers Created by Band-to Band Tunneling”, IEEE Electro Device Letters, VOL. 10, NO. 5, MAY (1989).

    Google Scholar 

  • C. Kittel, Introduction to Solid State Physic, John Wiley & Sons, New York, (1966).

    Google Scholar 

  • M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2”, J. of Applied Physics, vol. 40, pp. 273–283, (Jan. 1969).

    Google Scholar 

  • S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL flash EEPROM-Part I: performance and scaling”, IEEE Trans. Electron Devices, vol. ED-49, pp. 1296–1301, (July 2002).

    Google Scholar 

  • S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL flash EEPROM-Part I: reliability”, IEEE Trans. Electron Devices, vol. ED-49, pp. 1302–1307, (July 2002).

    Google Scholar 

  • Yohsuka Mochizucki, “Read-disturb Failure in Flash Memory at low field”, Intel reports, Nikkei Electronics Asia, pp. 35–36, (May 1993).

    Google Scholar 

  • J. Van Houdt, et al., “The HIMOS Flash technology: The alternative solution for low-cost embedded Mmeory”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 627–635, (April 2003).

    Google Scholar 

  • Samuel Tuan Wang, “On the I-V characteristics of Floating-Gate Mos transistors”, IEEE Transaction on electron devices, Vol ED-26, No 9, September (1979).

    Google Scholar 

Download references

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

(2005). The MOSFET Transistor and the Memory Cell. In: VLSI-Design of Non-Volatile Memories. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-26500-7_3

Download citation

  • DOI: https://doi.org/10.1007/3-540-26500-7_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-20198-4

  • Online ISBN: 978-3-540-26500-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics