Skip to main content

Competitive Analysis of Flash-Memory Algorithms

  • Conference paper
Algorithms – ESA 2006 (ESA 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4168))

Included in the following conference series:

Abstract

The cells of flash memories can only endure a limited number of write cycles, usually between 10,000 and 1,000,000. Furthermore, cells containing data must be erased before they can store new data, and erasure operations erase large blocks of memory, not individual cells. To maximize the endurance of the device (the amount of useful data that can be written to it before one of its cells wears out), flash-based systems move data around in an attempt to reduce the total number of erasures and to level the wear of the different erase blocks. This data movement introduces interesting online problems called wear-leveling problems. We show that a simple randomized algorithm for one problem is essentially optimal. For a more difficult problem, we show that clever offline algorithms can improve upon naive approaches, but online algorithms essentially cannot.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Assar, M., Nemazie, S., Estakhri, P.: Flash memory mass storage architecture incorporation wear leveling technique. US patent 5,479,638, US patent 5,388,083 (slightly different title), and US patent 5,485,595 (slightly different title), all filed 1993, issued 1995/6, and assigned to Cirrus Logic (1993)

    Google Scholar 

  2. Ban, A.: Wear leveling of static areas in flash memory. US patent 6,732,221, filed 2001, issued 2004, and assigned to M-Systems (2001)

    Google Scholar 

  3. Ben-Aroya, A.: Competitive analysis of flash-memory algorithms. Master’s thesis, School of Computer Science, Tel-Aviv University (April 2006), Available online at: http://www.tau.ac.il/~abrhambe

  4. Bruce, R.H., Bruce, R.H., Cohen, E.T., Christie, A.J.: Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volitile flash ram mass storage. US patent 6,000,006, Filed August 25, 1997; Issued December 7, 1999; Assigned to BIT Microsystems (December 1999)

    Google Scholar 

  5. Chiang, M.-L., Chang, R.-C.: Cleaning policies in mobile computers using flash memory. The Journal of Systems and Software 48(3), 213–231 (1999)

    Article  Google Scholar 

  6. Chiang, M.-L., Lee, P.C.H., Chang, R.-C.: Using data clustering to improve cleaning performance for flash memory. Software—Practice and Experience 29(3) (1999)

    Google Scholar 

  7. Estakhri, P., Assar, M., Reid, R., Alan, Iman, B.: Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volitile mass storage memory. US patent 5,835,935, Filed September 13, 1995; Issued November 10, 1998; Assigned to Lexar Media (1998)

    Google Scholar 

  8. Gal, E., Toledo, S.: Algorithms and data structures for flash memories. ACM Computing Surveys 37, 138–163 (2005)

    Article  Google Scholar 

  9. Han, S.-W.: Flash memory wear leveling system and method. US patent 6,016,275, Filed November 4, 1998; Issued January 18, 2000; Assigned to LG Semiconductors (January 2000)

    Google Scholar 

  10. Jou, E., Jeppesen III, J.H.: Flash memory wear leveling system providing immediate direct access to microprocessor. US patent 5,568,423, Filed April 14, 1995; Issued October 22, 1996; Assigned to Unisys (October 1996)

    Google Scholar 

  11. Kawaguchi, A., Nishioka, S., Motoda, H.: A flash-memory based file system. In: Proceedings of the USENIX 1995 Technical Conference, pp. 155–164, New Orleans, Louisiana (January 1995)

    Google Scholar 

  12. Lofgren, K.M.J., Norman, R.D., Thelin, G.B., Gupta, A.: Wear leveling techniques for flash EEPROM systems. US patent 6,081,447 and US patent 6,594,183, filed 1998/1999, issued 2000/2003, and assigned to Western Digital and Sandisk (1998)

    Google Scholar 

  13. Wells, S.E.: Method for wear leveling in a flash EEPROM memory. US patent 5,341,339, Filed November 1, 1993; Issued August 23, 1994; Assigned to Intel. (1994)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Ben-Aroya, A., Toledo, S. (2006). Competitive Analysis of Flash-Memory Algorithms. In: Azar, Y., Erlebach, T. (eds) Algorithms – ESA 2006. ESA 2006. Lecture Notes in Computer Science, vol 4168. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11841036_12

Download citation

  • DOI: https://doi.org/10.1007/11841036_12

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-38875-3

  • Online ISBN: 978-3-540-38876-0

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics