Abstract
In this article we describe a system based on a 32-bit processor, Leon, complete with security features offered by a specific cryptographic AES IP. Hardening is done not only on the principal hardware components but on the operating system as well, with attention for possible interaction between the different levels. The cryptographic IP is protected too to offer good resistance against, for example, fault-based attacks.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Lenstra, A.K.: Memo on RSA Signature Generatio. In The Presence of Faults. Private communication (available from the author), September 28 (1996)
Gaisler Research Homepage regularly updated, http://www.gaisler.com
Red Hat, eCos, updated on a regular basis Homepage, http://sources.redhat.com/ecos/
Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L.: Reconfigurable Hardware in Wearable Computing Nodes. In: 6th International Symposium on Wearable Computers (ISWC) 2002, pp. 215–222. IEEE, Los Alamitos (2002)
AMBA Homepage regularly updated, http://www.arm.com/products/solutions/AMBAHomePage.html
Gaisler, J.: A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture. In: DSN 2002, pp. 409-415 (2002)
Atmel Rad-Hard Product portal regularly updated, http://www.atmel.com/products/radhard/
Hwang, D., Schaumont, P., Fan, Y., Hodjat, A., Lai, B., Sakiyama, K., Yang, S., Verbauwhede, I.: Design Flow for HW/SW Accelleration Transparency in the Thumbpod Secure Embedded System. In: 40th Design Automation Conference (DAC 2003), Anahiem, California, June 2-6 (2003)
Hager, C.T., Midkiff, S.F.: An analysis of Bluetooth security vulnerabilities. In: Wireless Communications and Networking, (WCNC 2003), March 16-20, vol.3, pp. 1825–1831 (2003)
Ko, S.-B., Lo, J.-C.: Efficient Realization of Parity Prediction Functions in FPGAs. Journal of Electronic Testing Theory and Applications (JETTA) 20(5), 489–499 (2004)
Portolan, M., Leveugle, R.: A Highly Flexible Hardened RTL Processor Core Based on LEON. To be published at the Eight European Conference on Radiation and Its Effects on Components and Systems (RADECS 2005), September 19-23 (2005)
Portolan, M., Leveugle, R.: Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. In: 10th International On-Line Testing Symposium 2004 (IOLTS 2004), Madeira, Portugal, July 12-14 (2004)
Portolan, M., Leveugle, R.: A Context-Switch Based Checkpoint and Rollback Scheme. In: XIX Conference on Design of Circuits and Integrated Systems (DCIS 2004), Bordeaux, France, November 24-26 (2004)
NIST AES Homepage regularly up-dated, http://csrc.nist.gov/CryptoToolkit/tkencryption.html
Touba, N.A., McCluskey, E.J.: Logic Synthesis of Multilevel Circuits with Concurrent Error Detection. IEEE Transactions on Computer-Aided Design 16(7), 783–789 (1997)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Portolan, M., Leveugle, R. (2005). Towards a Secure and Reliable System. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds) Embedded and Ubiquitous Computing – EUC 2005. EUC 2005. Lecture Notes in Computer Science, vol 3824. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596356_108
Download citation
DOI: https://doi.org/10.1007/11596356_108
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30807-2
Online ISBN: 978-3-540-32295-5
eBook Packages: Computer ScienceComputer Science (R0)