Abstract
Reactive processors are a version of processors that provide architectural supports for the execution of reactive embedded applications. Even though much work has been done to improve the performance of reactive processors, the issue of optimizing power consumption has not been addressed. In this paper, we propose a new power-efficient processor core for reactive embedded applications. The new processor core (called ReMIC-PA) is implemented by adopting several power consumption optimizations to an existing reactive processor core (ReMIC). Initial benchmarking results show that ReMIC-PA achieves more than 20% power saving for data-dominated embedded applications and more than 50% power saving for control-dominated embedded applications when compared to ReMIC.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Antoniotti, M., Ferrari, A., Lavagno, L., Sangiovanni-Vincentelli, A., Sentovich, E.: Embedded system design specification: merging reactive control and data computation. In: Proceedings of the 40th IEEE Conference on Decision and Control, vol. 4, pp. 3302–3307 (2001)
Salcic, Z., Roop, P., Biglari-Abhari, M., Bigdeli, A.: Reflix: A processor core for reactive embedded applications. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 945–954. Springer, Heidelberg (2002)
Roop, P.S., Salcic, Z., Biglari-Abhari, M., Bigdeli, A.: A new reactive processor with architectural support for control dominated embedded systems. In: Proceedings of 16th International Conference on VLSI Design, pp. 189–194 (2003)
Roop, P.S., Salcic, Z., Dayaratne, M.W.S.: Towards direct execution of esterel programs on reactive processors. In: Proceedings of the 4th ACM International Conference on Embedded Software, Pisa, Italy (2004)
Berry, G.: The Exterel v5 Language Primer (2000)
Hui, D.: A reactive micro-architecture with task level concurrency support. Master’s thesis, Dept. of Electrical and Computer Engineering, University of Auckland (2004)
George, V., Rabaey, J.M.: Low-energy FPGAs: architecture and design. Kluwer Academic Publishers, Dordrecht (2001)
Poon, K.K.W., Yan, A., Wilton, S.J.E.: A flexible power model for fpgas. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 312–321. Springer, Heidelberg (2002)
Cadenas, O., Megson, G.: A clocking technique with power savings in virtex-based pipelined designs. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 322–331. Springer, Heidelberg (2002)
Papachristou, C.A., Nourani, M., Spining, M.: A multiple clocking scheme for low-power rtl design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7, 266–276 (1999)
Xunwei, W., Pedram, M.: Low power sequential circuit design using priority encoding and clock gating. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2000), pp. 143–148 (2000)
Petrov, P., Orailogulu, A.: Low-power instruction bus encoding for embedded processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, 812–826 (2004)
Chabini, N., Wolf, W.: Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, 573–589 (2004)
Hashimoto, M., Onoedera, H., Tamaru, K.: Input reordering for power and delay optimization. In: Proceedings of Tenth Annual IEEE International ASIC Conference and Exhibit, pp. 194–199 (1997)
Salcic, Z., Hui, D., Roop, P., Biglari-Abhari, M.: Remic - design of a reactive embedded microprocessor core. In: Proceedings of ASP-DAC (2005)
Yang, L.: Low-power implementation of a processor core with architectural support for reactive embedded applications. Master’s thesis, Dept. of Electrical and Computer Engineering, University of Auckland (2005)
Altera: Cyclone Handbook, Chapter 6, Using PLL in Cyclone Device (2004), http://www.altera.com/literature/hb/cyc/cyc_c51006.pdf
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Yang, L., Biglari-Abhari, M., Salcic, Z. (2005). A Power-Efficient Processor Core for Reactive Embedded Applications. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_12
Download citation
DOI: https://doi.org/10.1007/11572961_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29643-0
Online ISBN: 978-3-540-32108-8
eBook Packages: Computer ScienceComputer Science (R0)