Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
G. Geannopoulos, X. Dai — “An adaptive digital deskewing circuit for clock distribution networks”, ISSCC Digest of Technical Papers, 1998, Pg 400–401
N. Kurd, et al, — “A multi-GHz clocking scheme for the Pentium® 4 microprocessor”, IEEE Journal of Solid-State Circuits, Nov. 2001, Pg 1647–1653
P. Gronowski, et al, “High-performance microprocessor design”, IEEE Journal of Solid-State Circuits, May 1998, Pg 676–686
P. Restle, et al, — “The clock distribution of the Power 4 microprocessor”, ISSCC Digest of Technical Papers, 2002, Pg 144–145
S. Tam, et al, — “Clock generation and distribution for the first IA-64 microprocessor”, IEEE Journal of Solid-State Circuits, Nov. 2000, Pg 1545–1552
T. Xanthopoulos, et al, — “The design and analysis of the clock distribution network for a 1.2GHz Alpha microprocessor”, ISSCC Digest of Technical Papers, 2001, Pg 402–403
H. Kojima, et al, — “Half-swing clocking scheme for 75% power saving in clocking circuitry”, IEEE Journal of Solid-State Circuits, April 1995, Pg 432–435
H. Kawaguchi, T. Sakurai, — “A reduced clock-swing flip-flop (RCSFF) for 63% power reduction”, IEEE Journal of Solid-State Circuits, May 1998, Pg 807–811
M. Tokumasu, et al, — “A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)”, Custom Integrated Circuits Conference, 2002, Pg 129–132
M. Hamada, et al, — “Flip-flop selection technique for power-delay trade-off”, ISSCC Digest of Technical Papers, 1999, Pg 270–271
N. Nedovic, et al, “A low power symmetrically pulsed dual edge-triggered flip-flop”, ESSCIRC Proceedings, 2002
H. Mizuno, et al, — “A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators”, ISSCC Digest of Technical Papers, 1998, Pg 404–405
V. Gutnik, et al, — “Active GHz clock network using distributed PLLs”, ISSCC Digest of Technical Papers, 2000, Pg 174–175
J. Wood, et al, — “Multi-gigahertz low-power low-skew rotary clock scheme”, ISSCC Digest of Technical Papers, 2001, Pg 400–401
F. O’Mahony, et al., — “10GHz clock distribution using coupled standing-wave oscillators”, ISSCC Digest of Technical Papers, 2003, Pg 428–429
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer Science + Business Media, Inc.
About this chapter
Cite this chapter
Rusu, S. (2005). Clock Distribution for High Performance Designs. In: Nurmi, J., Tenhunen, H., Isoaho, J., Jantsch, A. (eds) Interconnect-Centric Design for Advanced SoC and NoC. Springer, Boston, MA. https://doi.org/10.1007/1-4020-7836-6_5
Download citation
DOI: https://doi.org/10.1007/1-4020-7836-6_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7835-4
Online ISBN: 978-1-4020-7836-1
eBook Packages: EngineeringEngineering (R0)