Skip to main content

Conclusions

In this chapter we studied principles for system-level interconnect modeling. The main focus was to examine global wires that distribute signals between di erent system blocks. Additionally, power distribution was dealt with in the end of the chapter by using the maximum allowed power supply voltage variation as a constraint to design power distribution network in a proper way. We examined electrical properties of on-chip wires and discussed shortly some possible interconnect schemes in SoC and NoC. Some interconnect schemes in SoC and NoC were shortly discussed. We used Rent’s rule and multiple Rent’s exponents to evaluate cost functions that di erent system blocks set for the global wiring (both signal and power distribution). We optimized our signaling to achieve the maximum bandwidth, the minimum delay by using properly sized and placed repeaters and finally presented a joint optimization case study in which both power distribution and signal distribution in global wires were simultaneously optimized. Our analysis revealed that both early cost/performance estimation of resources (i.e. functional blocks) and the joint optimization of global signal and power estimation are essential when designing future SoCs and NoCs.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. D. Pamunuwa, L. R. Zheng, and H. Tenhunen. Maximising throughput over parallel wire structures in the deep submicrometer regime. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(2):224–243, April 2003.

    Article  Google Scholar 

  2. E. Chiprout. Interconnect and substrate modeling and analysis: An overview. IEEE Journal of Solid-State Circuits, 33:1445–1452, September 1998.

    Article  Google Scholar 

  3. K. L. Shepard, D. Sitaram, and Y. Zheng. Full-chip, three-dimensional, shapes-based RLC extraction. In Proceedings of IC-CAD, pages 142–149, November 2000.

    Google Scholar 

  4. J. M. Rabaey. Digital Integrated Circuits. Prentice-Hall, Upper Saddle River, NJ, 1996.

    Google Scholar 

  5. E. Barke. Line-to-ground capacitance calculation for VLSI: a comparison. EEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 7(2):295–298, February 1988.

    Google Scholar 

  6. C. P. Yuan and T. N. Trick. A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuits. IEEE Electron Device Letters, EDL-3:391–393, 1982.

    Google Scholar 

  7. L. R. Zheng, D. Pamunuwa, and H. Tenhunen. Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep sub-micron VLSI design. In Proceedings of European Solid-State Circuit Conference, pages 324–327, 2000.

    Google Scholar 

  8. W. C. Elmore. The transient response of linear damped circuits. Journal of Applied Physics, 19:55–63, January 1948.

    Article  Google Scholar 

  9. J. Rubinstein, P. Penfield, and M. Horowitz. Signal delay in RC tree networks. IEEE Transactions on Computer-Aided Design, CAD-2(3): 202–211, July 1983.

    Google Scholar 

  10. H. B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Reading, MA, 1990.

    Google Scholar 

  11. T. Sakurai. Approximation of wiring delay in MOSFET LSI. IEEE Journal of Solid-State Circuits, 18:418–426, August 1983.

    Article  Google Scholar 

  12. C. R. Paul. Analysis of Multi-Conductor Transmission Lines. John Wiley and Sons, New York, NY, 1994.

    Google Scholar 

  13. W. J. Dally and J. W. Poulton. Digital Systems Engineering. Cambridge University Press, New York, NY, 1998.

    Google Scholar 

  14. H. Kawaguchi and T. Sakurai. Delay and noise formulas for capacitively coupled distributed RC lines. In Proceedings of Asian and South Pacific Design Automation Conference, pages 35–43, June 1998.

    Google Scholar 

  15. A. B. Kahng, S. Muddu, and E. Sarto. On switch factor based analysis of coupled RC interconnects. In Proceedings of DAC, pages 79–84, June 2000.

    Google Scholar 

  16. B. S. Landman and R. L. Russo. On a pin versus block relationship for partitions of logic graphs. IEEE Transactions on Computers, C20(12):1469–1479, December 1971.

    Google Scholar 

  17. W. Donath. Placement and average interconnection lengths of computer logic. IEEE Transactions on Circuits and Systems, CAS-26(4):272–277, April 1979.

    Google Scholar 

  18. A. Caldwell, Y. Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov, M. Oliver, D. Stroobandt, and D. Sylvester. GTX: The MARCO GSRC technology exploration system. In Proceedings in 37th IEEE/ACM Design Automation Conference, pages 693–698, Los Angeles, 6 2000. ACM Press.

    Google Scholar 

  19. J. C. Principe, N. R. Euliano, and W. C. Lefebvre. Neural and Adaptive Systems: Fundamentals through Simulations. Wiley & Sons, Inc, 2000.

    Google Scholar 

  20. T. Ahonen, T. Nurmi, J. Nurmi, and J. Isoaho. Block-wise extraction of Rent’s exponents for an extensible processor. In IEEE Computer Society Annual Symposium on VLSI, pages 193–199, February 2003.

    Google Scholar 

  21. J. A. Davis and J. D. Meindl. Generic models for interconnect delay across arbitrary wire-tree networks. In Proceedings of Interconnect Technology Conference, pages 129–131, 2000.

    Google Scholar 

  22. A. Deutsch, P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Crauter, D. C. Edelstein, and P. J. Restle. On-chip wiring design challenges for gigahertz operation. Proceedings of the IEEE, 89(4):529–555, April 2001.

    Article  Google Scholar 

  23. R. Ho, K. W. Mai, and M. Horowitz. The future of wires. Proceedings of the IEEE, 89(4), April 2001.

    Google Scholar 

  24. SEMATECH. International technology roadmap for semiconductors. http://public.itrs.net/files/1999_SIA_Roadmap/Home.htm, 1999.

  25. G. A. Sai-Halasz. Performance trends in high-end processors. Proceedings of the IEEE, 83(1), January 1995.

    Google Scholar 

  26. L. R. Zheng and H. Tenhunen. Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits. In Proceedings of IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging, pages 307–310, 2000.

    Google Scholar 

  27. Y. L. Low, L. W. Schaper, and S. S. Ang. Modeling and experimental verification of the interconnected mesh power system (IMPS) MCM topology. IEEE Transactions on Components, Packaging, and Manufacturing Technology part B, 20:42–49, February 1997.

    Article  Google Scholar 

  28. R. R. Tummala. Microelectronic Packaging Handbook, 2nd edition. Chapman & Hall, 1997.

    Google Scholar 

  29. T. Nurmi, L. R. Zheng, J. Isoaho, and H. Tenhunen. Early estimation of interconnect e ects on the operation of System-on-Chip platforms. In Proceedings of the 15th European Conference on Circuit Theory and Design (ECCTD’01), August 2001.

    Google Scholar 

  30. S. Virtanen, J. Lilius, and T. Westerlun. A processor architecture for the TACO protocol processor development environment. In Proceedings of the 18th IEEE NORCHIP Conference, pages 204–211, November 2000.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer Science + Business Media, Inc.

About this chapter

Cite this chapter

Nurmi, T. et al. (2005). Global Interconnect Analysis. In: Nurmi, J., Tenhunen, H., Isoaho, J., Jantsch, A. (eds) Interconnect-Centric Design for Advanced SoC and NoC. Springer, Boston, MA. https://doi.org/10.1007/1-4020-7836-6_3

Download citation

  • DOI: https://doi.org/10.1007/1-4020-7836-6_3

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4020-7835-4

  • Online ISBN: 978-1-4020-7836-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics