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References
H. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990
H. H. Chen and J. S. Neely. “Interconnect and Circuit Modeling Techniques for Full-Chip Power Supply Noise Analysis”, in IEEE Transactions on Components, Packaging, and Manufacturing Technology-part B, Vol. 21, No.3, August 1998.
K. L. Shepard and V. Narayanan. “Noise in Deep Submicron Digital Design”, In Proc. of International Conference on Conputer Aided Design (ICCAD), 1999.
H. H. Chen and D. D. Ling. “Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design”, in Proc. of Design Automation Conference, Anaheim, California, 1997.
W. J. Dally and J. W. Poulton. Digital Systems Engineering, Cambridge University Press, 1998.
C. L. Seitz. “System timing” Chapter 7 in Mead and Conway, editors, Introduction to VLSI Systems, Addison-Wesley, 1980.
A. Davis and S. M. Nowick. “Asynchronous circuit design: motivation, back-ground and methods.” In G. Birtwistle and A. Davis, editors, Asynchronous Digital Circuit Design, Springer, 1995.
I. E. Sutherland. “Micropipelines. The 1988 Turing Award Lecture”, Communications of the ACM, Vol. 32, No.6, pp. 720–738, June 1989.
A.M.G. Peeters. Single-Rail Handshake Circuits. Ph.D. Thesis, Eindhoven University of Technology, The Netherlands, 1996.
J. Sparso and S. Furber. Principles of Asynchronous Circuit Design-A System Perspective. Kluwer Academic Publishers, 2001.
Tom Verhoe. “Delay-insensitive codes-an overview”, Distributed computing, 3(1):1–8, 1988.
W. J. Bainbridge and S. B. Furber. “Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding”,in Proc. of International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2001.
S. Hayashi and M. Yamada. “EMI-Noise Analysis Under ASIC Design Environment”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No.11, November 2000.
D. M. Chapiro. Globally-Asynchronous Locally-Synchronous Systems. Ph.D. thesis, Stanford University, October 1984.
P. Liljeberg, J. Plosilaand J. Isoaho. “Asynchronous Interface for Locally Clocked Modulesin ULSI Systems”,in Proc. of International Symposium on Circuits and Systems (ISCAS), Sydney, Australia, May 2001.
J. Muttersbach, T. Villiger and W. Fichtner. “Practical Design of Globally-Asynchronous Locally-Synchronous Systems”, in Proc. of International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), April 2000.
P. Liljeberg, J. Plosila and J. Isoaho. “Self-Timed Ring Architecture for SoC Applications” in Proc. of IEEE International SoC Conference, Portland, OR, USA, September 2003.
L. T. Pillage and R. R. Rohrer. “Asymptotic Waveform Evaluation for Timing Analysis”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No.4, pp. 352–366, April 1990.
A. Devgan. “E cient Coupled Noise Estimation for On-Chip Interconnects” in IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, USA, 1997.
M. Becer and I. N. Hajj. “An Analytical Model for Delay and Crosstalk Estimation in Interconnects under General Switching Conditions”, in the 7th IEEE International Conference on Electronics, Circuits and Systems, Kaslik, Lebanon, 2000.
S. Tuuna and J. Isoaho. “Estimation of Crosstalk Noise for On-Chip Buses” in Proc. of 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, Turin, Italy, September 2003.
H. Kawaguchi and T. Sakurai. “Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines” in Proc. of Asia and South Pacific Design Automation Conference, Yokohama, Japan, 1998.
P. Sotiriadis and A. Chandrakasan. “Reducing Bus Delay in Submicron Technology Using Coding”, in Proc. of IEEE Asia and South Pacific Design Automation Conference, 2001.
K. Hirose and H. Yasuura. “A Bus Delay Reduction Technique Considering Crosstalk”, in Proc. of the Design Automation and Test in Europe, 2000.
J. Plosila, P. Liljeberg and J. Isoaho. “Pipelined On-Chip Bus Architecture with Distributed Self-Timed Control”, in Proc. of IEEE International Symposium on Signals, Circuits and Systems (SCS), Iasi, Romania, 2003.
M. S. Ryan and G. R. Nudd. “The Viterbi Algorithm”, Warwick Research Report, No.238, University of Warwick, England, February 1993.
T. K. Moon and W. C. Stirling. Mathematical Methods and Algorithms for Signal Processing, Prentice Hall, 2000.
P. A. Riocreux, L. E. M. Brackenbury, M. Cumpstey and S. Furber. “A Low-Power Self-Timed Viterbi Decoder” in Proc. of International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2001.
M. Savolainen. Reusable Viterbi Decoder Implementation, M.Sc. Thesis, Tampere University of Technology, October 2001.
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Liljeberg, P., Tuominen, J., Tuuna, S., Plosila, J., Isoaho, J. (2005). Self-Timed Approach for Noise Reduction in NoC Reduction in NoC. In: Nurmi, J., Tenhunen, H., Isoaho, J., Jantsch, A. (eds) Interconnect-Centric Design for Advanced SoC and NoC. Springer, Boston, MA. https://doi.org/10.1007/1-4020-7836-6_11
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