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Arbitration and Routing Schemes for on-Chip Packet Networks

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Interconnect-Centric Design for Advanced SoC and NoC

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References

  1. L. Benini, and G. De Micheli, Networks on Chips: A New SoC Paradigm, Computer, 35(1): 70–78, 2002.

    Google Scholar 

  2. S.K. Tewksbury, M. Uppuluri, and L.A. Hornak, Interconnections/Micro-Networks for Integrated Microelectronics, Proceedings of GLOBECOM’92, Orlando, FL, USA, 1992, pages 180–186.

    Google Scholar 

  3. F.A. Tobagi, Fast Packet Switched Architectures for Broadband Integrated Services Digital Networks, Proceedings of the IEEE 78(1)(1990): 133–167.

    Article  Google Scholar 

  4. H. Ahmadi, and W.E. Denzel, A Survey of Modern High-Performance Switching Techniques, IEEE Journal of Selected Areas in Communications 7(7)(1989): 1091–1103.

    Article  Google Scholar 

  5. H.J. Chao, Next Generation Routers, Proceedings of the IEEE, 90(9)(2002): 1518–1558.

    Article  Google Scholar 

  6. E. Rijpkema, K.G.W. Goossens, A. Radulescu, J. Dielissen, J. van Meerberg, P. Wielage, and E. Waterlander, Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 2003), Messe Munich, Germany, 2003, pages 350–355.

    Google Scholar 

  7. P. Guerrier, and A. Greiner, A Generic Architecture for On-Chip Packet-Switched Interconnections, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 2000), Paris, France, 2000, pages 250–256.

    Google Scholar 

  8. P.P. Pande, C. Grecu, A. Ivanov, and R. Saleh, Design of a Switch for Network on Chip Applications, Proceedings of International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, 2003, pages 217–220.

    Google Scholar 

  9. Y. Tamir, and H.-C. Chi, Symmetric Crossbar Arbiters for VLSI Communication Switches, IEEE Transactions on Parallel and Distributed Systems 4(1) (1993) 13–27.

    Article  Google Scholar 

  10. P. Kermani, and L. Kleinrock, Virtual Cut-Through: A New Computer Communication Switching Technique, Computer Networks 3(4) (1979): 267–286.

    MathSciNet  Google Scholar 

  11. W.J. Dally, and C.L. Seitz, Deadlock-Free Message Routing in Multicomputer Interconnecion Networks, IEEE Transactions on Computers C-36(5) (1987): 547–553.

    Google Scholar 

  12. W.J. Dally, Virtual-Channel Flow Control, Proceedings of 17th Annual International Symposium on Computer Architecture, Seattle, WA, USA, 1990, pages 60–68.

    Google Scholar 

  13. N. McKeown, Scheduling Algorithms for Input-Queued Cell Switches, Ph.D. Thesis, University of California at Berkley, 1995.

    Google Scholar 

  14. N. McKeown, The iSLIP Scheduling Algorithm for Input Queued Switches, IEEE/ACM Transactions on Networking 7(2)(1999): 188–201.

    Article  Google Scholar 

  15. H.J. Chao, Saturn: A Terabit Packet Switch Using Dual Round-Robin, Proceedings of Global Telecommunications Conference (GLOBECOM 2000), San Francisco, CA, USA, 2000, pages 487–495.

    Google Scholar 

  16. E. Oki, R. Rojas-Cessa, and H.J. Chao, PMM: A Pipelined Maximal-Sized Matching Scheduling Approach for Input-Buffered Switches, Proceedings of Global Telecommunications Conference (GLOBECOM 2001), San Antonio, TX, USA, 2001, pages 35–39.

    Google Scholar 

  17. J. Hurt, A. May, X. Zhu, and B. Lin, Design and Implementation of High-Speed Symmetric Crossbar Schedulers, Proceedings of IEEE International Conference on Communications, Vancouver, BC, Canada, 1999, pages 1478–1483.

    Google Scholar 

  18. A. Mekkittikul, and N. McKeown, A Practical Scheduling Algorithm to Achieve 100% Throughput in Input-Queued Switches, Proceedings of the 17th Annual Joint Conference of IEEE Computer and Communications Societies (INFOCOM 1998), San Francisco, CA, USA, 1998, pages 792–799.

    Google Scholar 

  19. Z. Lisheng, and H. Chengdu, A Practical Scheduling Algorithm for Input Buffered Switch, Proceedings of International Conference on Communication Technology (ICCT 2000), Beijing, China, 2000, pages 1059–1064.

    Google Scholar 

  20. D.E. Culler, J. Pal Singh, and A. Gupta, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann Publishers Inc. San Francisco, USA, 1999.

    Google Scholar 

  21. M.D. Schroeder, A.D. Birrel, M. Burrows, H. Murray, R.M. Needham, T.L. Rodeheffer, E.H. Satterthwaite, and C.P. Thacker, Autonet: A High-Speed, Self-Configuring Local Area Network Using Point-to-Point Links, IEEE Journal on Selected Areas in Communications, 9(8) (1991): 1318–1335.

    Article  Google Scholar 

  22. N.J. Boden, D. Cohen, R.E. Felderman, A.E. Kulawik, C.L. Seitz, J.N. Seizovic, and S. Wen-King, Myrinet: A Gigabit-per-Second Local Area Network, IEEE Micro 15(1)(1995): 29–36.

    Article  Google Scholar 

  23. J.C. Sancho, A. Robles, and J. Duato, On the Relative Behaviour of Source and Distributed Routing in NOWs Using Up*/Down* Routing Schemes, Proceedings of the 9th Euromicro Workshop on Parallel and Distributed Processing, Mantova, Italy, 2001, pages 11–18.

    Google Scholar 

  24. W. Qiao, and L.M. Ni, Adaptive Routing in Irregular Networks Using Cut-Through Switches, Proceeding of the International Conference on Parallel Processing, Ithaca, NY, USA, 1996, pages 52–60.

    Google Scholar 

  25. H. Räcke, Minimizing Congestion in General Networks, Proceeding of the 43rd Annual IEEE Symposium on Foundations of Computer Science, Vancouver, Canada, 2002, pages 43–52.

    Google Scholar 

  26. Y. Azar, E. Cohen, A. Fiat, H. Kaplan, and H. Räcke, Optimal Oblivious Routing in Polynomial Time, Proceedings of the 35th ACM Symposium on Theory of Computing, San Diego, California, USA, 2003, pages 383–388.

    Google Scholar 

  27. N. Bansal, A, Blum, S. Chawla, and A. Meyerson, Online Oblivious Routing, Proceedings of the 15th Annual Symposium on Parallel Algorithms and Architectures, San Diego, California, USA, 2003, pages 44–49.

    Google Scholar 

  28. M. Bienkowski, M. Korzeniowski, and H. Räcke, A Practical Algorithm for Constructing Oblivious Routing Schemes, Proceedings of the 15th Annual ACM Symposium on Parallel Algorithms and Architectures, San Diego, California, USA, 2003, pages 24–33.

    Google Scholar 

  29. C.J. Glass, and L.M. Ni, The Turn Model for Adaptive Routing, Proceeding of the 19th Annual International Symposium on Computer Architecture, 1992, pages 278–287.

    Google Scholar 

  30. W.J. Dally, and H. Aoki, Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels, IEEE Transactions on Parallel and Distributed Systems 4(4)(1993): 466–475.

    Article  Google Scholar 

  31. G.D. Pifarre, L. Gravano, S.A. Felperin, and J.L.C. Sanz, Fully Adaptive Minimal Deadlock-Free Packet Routing in Hypercubes, Meshes, and Other Networks: Algorithms and Simulations, IEEE Transactions on Parallel and Distributed Systems, 5(3)(1994): 247–263.

    Article  Google Scholar 

  32. D.H. Linder, and J.C. Harden, An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes, IEEE Transactions on Computers 40(1)(1991): 2–12.

    Article  MathSciNet  Google Scholar 

  33. L.G. Valiant, and G.J. Brebner, Universal Schemes for Parallel Communication, Proceedings of the 13th Annual ACM Symposium on Theory of Computing, Milwaukee, Wisconsin, USA, 1981, pages 263–277.

    Google Scholar 

  34. B. Towles, W.J. Dally, and S. Boyd, Throughput Centric Routing Algorithm Design, Proceedings of the 15th Annual ACM Symposium on Parallel Algorithms and Architectures, San Diego, California, USA, 2003, pages 200–209.

    Google Scholar 

  35. L.M. Ni, Y. Gui, and S. Moore, Performance Evaluation of Switch Based Wormhole Networks, IEEE Transaction on Parallel and Distributed Systems, 8(5)(1997): 462–474.

    Google Scholar 

  36. S.R. Ohring, M. Ibel, S.K. Das, and M.J. Kumar, On Generalized Fat Trees, Proceedings of 9th International Parallel Processing Symposium, Santa Barbara, CA, USA, 1995, pages 37–44.

    Google Scholar 

  37. H. Kariniemi, and J. Nurmi, New Routing Algorithm for Improving the Throughput of Fat Tree Interconnection Networks, Proceedings of the IASTED International Conference on Computer Science and Technology, Cancun, Mexico, 2003, pages 375–381.

    Google Scholar 

  38. H. Kariniemi, and J. Nurmi, New Adaptive Routing Algorithm for Extended Generalized Fat Tree On-Chip, Proceedings of International Symposium on System-on-Chip 2003, Tampere, Finland, 2003, pages 113–118.

    Google Scholar 

  39. C.E. Leiserson, Fat Trees: Universal Networks for Hardware-Efficient Supercomputing, IEEE Transactions on Computers C-34(10)(1985): 892–901.

    Google Scholar 

  40. C.E. Leiserson, Z.S. Abuhamdeh, D.C. Douglas, C.R. Feynman, M.N. Ganmukhi, J.V. Hill, W.D. Hillis, B.C. Kuszmaul, M.A. St. Pierre, D.S. Wells, M.C. Wong, S.-W. Yang, R. Zak, The Network Architecture of the Connection Machine CM-5, Proceedings of the 4th Annual ACM Symposium on Parallel Algorithms and Architectures, San Diego, California, USA, 1992, pages 272–285.

    Google Scholar 

  41. J. Beecroft, M. Homewood, and M. McLaren, Meiko CS-2 Interconnect Elan-Elite Design, Parallel Computing 20(10–11) (1994): 1627–1638.

    Google Scholar 

  42. H. Sethu, C.B. Stunkel, and R.F. Stucke, IBM RS/6000 SP Interconnect Network Topologies for Large Systems, Proceedings of IEEE International Conference on Parallel Processing, Minneapolis, MN, USA, 1998, pages 620–627.

    Google Scholar 

  43. K.M. Khalil, K.Q. Luc, and D.V. Wilson, LAN Traffic Analysis and Workload Characterization, Proceedings of Conference on Local Computer Networks, Minneapolis, USA, 1990, pages 112–122.

    Google Scholar 

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Authors and Affiliations

  1. Institute of Digital and Computer Systems, Tampere University of Technology, Finland

    Heikki Kariniemi & Jari Nurmi

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  1. Heikki Kariniemi
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Editors and Affiliations

  1. Tampere University of Technology, Finland

    Jari Nurmi

  2. Royal Institute of Technology, Sweden

    Hannu Tenhunen  & Axel Jantsch  & 

  3. University of Turku, Finland

    Jouni Isoaho

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Kariniemi, H., Nurmi, J. (2005). Arbitration and Routing Schemes for on-Chip Packet Networks. In: Nurmi, J., Tenhunen, H., Isoaho, J., Jantsch, A. (eds) Interconnect-Centric Design for Advanced SoC and NoC. Springer, Boston, MA. https://doi.org/10.1007/1-4020-7836-6_10

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  • DOI: https://doi.org/10.1007/1-4020-7836-6_10

  • Publisher Name: Springer, Boston, MA

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  • Online ISBN: 978-1-4020-7836-1

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