Abstract
Multimedia intellectual property (IP) cores play a critical role in a successful multimedia SOC design. This chapter will focus on the design of image and video codec IPs, which usually requires lots of computational power. From theory to practice and from algorithm to hardware architecture, design methodologies toward an optimized architecture and also real design cases will be presented. Both top-down system analysis and bottom-up core module design are emphasized. Following theoretical discussions of the overall scenario, key building blocks of image and video codecs proposed in literature are reviewed. Examples will cover motion estimation, discrete cosine transform, discrete wavelet transform, and entropy coder. Then, complete image and video codec designs are explored. JPEG, JPEG 2000, and H.264/AVC are the three case studies. This chapter is intended to provide an overview, from theory to practice, on how to design efficient multimedia IPs
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References
ISO/IEC, Int. Standard DIS 10918, “Digital compression and coding of continuous-tone still images.”
ISO/IEC 15444-1:2000, “Information technology – JPEG 2000 image coding system – Part 1: Core coding system.”
ITU-T Recommendation H.264 and ISO/IEC 14496-10 AVC, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, 2003.
W. Kou, Digital image compression algorithms and standards, Norwell, MA: Kluwer Academic Publishers, 1995.
V. Bhaskaran and K. Konstantinides. Image and Video Compression Standards: Algorithms and Architectures. Norwell, MA: Kluwer Academic Publishers, 1997.
Y. Q. Shi, H. Sun, Image and Video Compression for Multimedia Engineering: Fundamentals, Algorithms, and Standards, CRC Press, 1999.
K. R. Rao and P. Yip, Discrete Cosine Transform: Algorithms, Advantages, Applications. New York: Academic, 1990.
W. P. Pennebaker and J. L. Mitchell, JPEG Still Image Data Compression Standard. New York: Van Nostrand Reinhold, 1992.
D. S. Taubman and M. W. Marcellin, JPEG2000 image compression fundamentals, standards and practice. Norwell, MA: Kluwer Academic Publishers, 2002.
P. Kuhn, “Acomplexity analysis tool: iprof (ver 0.41),” ISO/IEC JTC/SC29/WG11, Dublin (Ireland), Doc. M3551, July 1998.
Iain E.G. Richardson, Video codec design: developing image and video compression systems, Chichester: Wiley, 2002.
F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, L. Nachtergaele, and A. Vandecappele, Custom memory management methodology: exploration of memory organization for embedded multimedia system design, Norwell, MA: Kluwer Academic Publishers, 1998.
Y.-W. Huang, C.-Y. Chen, C.-H. Tsai, C.-F. Shen, and L.-G. Chen, “Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results” to Appear, IEEE Journal of VLSI Signal Processing.
Digital Video Coding Group, ITU-T recommendation H.263 software implementation, Telenor R&D, 1995.
W. Li and E. Salari, “Successive elimination algorithm for motion estimation,” IEEE Trans. Image Processing, vol. 4, no. 1, pp. 105-107, Jan. 1995.
M. Bierling, “Displacement estimation by hierarchical block matching,” Proc. of SPIE Visual Commun. Image Processing (VCIP’88), 1988, pp. 942-951.
B. Liu and A. Zaccarin, “New fast algorithms for the estimation of block motion vectors,” IEEE Trans. Circuits Syst. Video Technol., vol. 3, no. 2, pp. 148-157, Apr. 1993.
Z. L. He, C. Y. Tsui, K. K. Chan, and M. L. Liou, “Low-power VLSI design for motion estimation using adaptive pixel truncation,” IEEE Trans. Circuits Syst. Video Technol., vol. 10, no. 5, pp. 669-678, Aug. 2000.
J. Y. Tham, S. Ranganath, M. Ranganath, and A. A. Kassim, “A novel unrestricted center-biased diamond search algorithm for block motion estimation,” IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 4, pp. 369-377, Aug. 1998.
S. Zhu and K. K. Ma, “A new diamond search algorithm for fast blockmatching motion estimation,” IEEE Trans. Image Processing, vol. 9, no. 2, pp. 287-290, Feb. 2000.
A. M. Tourapis, O. C. Au, M. L. Liou, G. Shen, and I. Ahmad, “Optimizing the mpeg-4 encoder – advanced diamond zonal search,” Proc. of IEEE Int. Symp. Circuits Syst. (ISCAS’00), 2000, pp. 674-677.
A. M. Tourapis, O. C. Au, and M. L. Liu, “Highly efficient predictive zonal algorithms for fast block-matching motion estimation,” IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 10, pp. 934-947, Oct. 2002.
T. Koga, K. Iinuma, A. Hirano, Y. Iijima, and T. Ishiguro, “Motion compensated inter frame coding for video conferencing,” Proc. Nat. Telecom-mun. Conf., 1981, pp. C9.6.1-C9.6.5.
J. Jain and A. Jain, “Displacement measurement and its application in internal image coding,” IEEE Trans. Commun., vol. COM-29, no. 12, pp. 1799-1808, Dec. 1981.
M. J. Chen, L. G. Chen, and T. D. Chiueh, “One-dimensional full search motion estimation algorithm for video coding,” IEEE Trans. Circuits Syst. Video Technol., vol. 4, no. 5, pp. 504-509, June 1994.
R. Li, B. Zeng, and M. L. Liou, “A new three-step search algorithm for block motion estimation,” IEEE Trans. Circuits Syst. Video Technol., vol. 4, no. 4, pp. 438-442, Aug. 1994.
L. M. Po and W. C. Ma, “A novel four-step search algorithm for fast block motion estimation,” IEEE Trans. Circuits Syst. Video Technol., vol. 6, no. 3, pp. 313-317, June 1996.
L. K. Liu and E. Feig, “A block-based gradient descent search algorithm for block motion estimation in video coding,” IEEE Trans. Circuits Syst.Video Technol., vol. 6, no. 4, pp. 419-422, Aug. 1996.
Y.W. Huang, S. Y. Ma, C. F. Shen, and L. G. Chen, “Predictive line search: an efficient motion estimation algorithm for mpeg-4 encoding systems on multimedia processors,” IEEE Trans. Circuits and Syst. Video Technol., vol. 13, no. 1, pp. 111-117, Jan. 2003.
D. Tzovaras, M. G. Strintzis, and H. Sahinolou, “Evaluation of multiresolution block matching techniques for motion and disparity estimation,” Signal Processing: Image Commun., vol. 6, pp. 56-67, 1994.
J. H. Lee, K. W. Lim, B. C. Song, and J. B. Ra, “A fast multi-resolution block matching algorithm and its VLSI architecture for low bit-rate video coding,” IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 12, pp. 1289-1301, Dec. 2001.
K. M. Yang, M. T. Sun, and L. Wu, “A family of VLSI designs for the motion compensation block-matching algorithm,” IEEE Trans. Circuits Syst., vol. 36, no. 2, pp. 1317-1325, Oct. 1989.
T. Komarek and P. Pirsch, “Array architectures for block matching algorithms,” IEEE Trans. Circuits Syst., vol. 36, no. 2, pp. 1301-1308, Oct. 1989.
Y. S. Jehng, L. G. Chen, and T. D. Chiueh, “An efficient and simple VLSI tree architecture for motion estimation algorithms,” IEEE Trans. Signal Processing, vol. 41, no. 2, pp. 889-900, Feb. 1993.
W.-M. Chao, C.-W. Hsu, Y.-C. Chang, and L.-G. Chen, “A novel motion estimator supporting diamond search and fast full search,” Proc. of IEEE Int. Symp. Circuits Syst. (ISCAS’02), 2002, pp. 492-495.
M.-Y. Hsu, “Scalable module-based architecture for MPEG-4 BMA motion estimation,” M.S. thesis, National Taiwan Univ., June 2000.
J.-C. Tuan, T.-S. Chang, and C.-W. Jen, “On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture,” IEEE Trans. CSVT, vol. 12, no. 1, pp. 61-72, Jan. 2002.
C.-T. Huang, C.-Y. Chen, Y.-H. Chen, and L.-G. Chen, “Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.
A. Madisetti and A. N. Willson, “A 100 MHz 2-D 8$× $8 DCT/IDCT processor for HDTV applications,” IEEE Trans. Circuits Syst. Video Technol., vol. 5, no. 2, pp. 158-165, Apr. 1995.
W. Chen et al., “A fast computational algorithm for the discrete cosine transform,” IEEE Trans. Commun., vol. COM-25, pp. 1004-1009, Sept. 1977.
G. S. Taylor and G. M. Blair, “Design for the discrete cosine transform in VLSI,” IEE Proc. Comput. Digit. Tech., vol. 145, no. 2, pp. 127-133, Mar. 1998.
M. Kovac and N. Ranganathan, “JAGUAR: a full pipelined VLSI architecture for JPEG image compression standard,” Proc.of the IEEE, vol. 83, no. 2, pp.247-258, Feb. 1995.
C.-T. Huang, P.-C.Tseng, L.-G. Chen, “Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform,” IEEE Trans. Signal Processing, vol. 53, no. 4, pp. 1575-1586, Apr. 2005.
C.-J. Lian, H.-C. Chang, K.-F. Chen, and L.-G. Chen, “A JPEG decoder IP Core supporting user-defined Huffman table decoding,” Proc. of the 9th International Symposium on Integrated Circuits, Devices and Systems (ISIC-2001), Singapore, pp. 497-500, Sep. 2001.
S.-M. Lei and M.-T. Sun, “An entropy coding system for digital HDTV applications,” IEEE Trans. Circuits Syst. Video Technol., vol. 1, no. 1, pp. 147-155, Mar. 1991.
C.-J. Lian, L.-G. Chen, H.-C. Chang, and Y.-C. Chang, “Design and implementation of JPEG encoder IP core,” Proc. of Asia and South Pacific Design Automation Conf. (ASP-DAC 2001), Yokohama, Japan, pp. 29-30, Jan 2001.
H.-C. Fang, et al., “81MS/s JPEG2000 single-chip encoder with rate-distortion optimization,” Digest of Technical Papers, 2004 IEEE International Solid-State Circuits Conference (ISSCC 2004), pp. 328-531 Vol.1
C.-J. Lian, K.-F. Chen, H.-H. Chen, and L.-G.Chen, “Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000,” IEEE Trans. Circuits and Syst. For Video Technol., vol. 13, no. 3, pp. 219-230, Mar. 2003.
H. Yamauchi, S. Okada, K. Taketa, T. Ohyama, Y. Matsuda, T. Mori, S. Okada, T. Watanabe, Y. Matsuo, Y. Yamada, T. Ichikawa, Y. Matsushita, “Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications,” Digest of Technical Papers, 2003 IEEE International Solid-State Circuits Conference (ISSCC 2003), pp. 476-477 vol.1.
K. Andra, C. Chakrabarti, T. Acharya, “A high-performance JPEG2000 architecture,” IEEE Trans. Circuits and Systems for Video Technology, Vol. 13, no. 3, pp. 209-218, Mar. 2003.
B.-F. Wu, C.-F. Lin, “An efficient architecture for JPEG2000 coprocessor,” IEEE Trans. on Consumer Electronics, vol. 50, no. 4, pp. 1183-1189, Nov. 2004.
H. Yamauchi, S. Okada, K. Taketa, Y. Matsuda, T. Mori, T. Watanabe, Y. Matsuo, Y. Matsushita, “1440 $× $ 1080 pixel, 30 frames per second motion-JPEG 2000 codec for HD-movie transmission,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 331-341, Jan. 2005.
T. Wiegand, G. J. Sullivan, G. Bjntegaard, A. Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Trans. on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 560-576, Jul. 2003.
J. Ostermann, J. Bormans, P. List, D. Marpe, M. Narroschke, F. Pereira, T. Stockhammer, T. Wedi, “Video coding with H.264/AVC: tools, performance, and complexity,” IEEE Magazine on Circuits and Systems, vol. 4, no. 1, pp. 7-28, first quarter, 2004.
A. Puri, X. Chen, and A. Luthra, “Video coding using the H.264/MPEG-4 AVC compression standard,” Trans. on Signal Processing: Image Communication, vol. 19, no. 9, pp. 793-849, Oct. 2004.
A. Joch, F. Kossentini, H. Schwarz, T. Wiegand, and G. J. Sullivan, “Performance comparison of video coding standards using Lagragian coder control,” Proc. of 2002 International Conference on Image Processing (ICIP 2002), 2002, pp. 501-504.
Y.-W. Huang, T.-C. Chen, C.-H. Tsai, C.-Y. Chen, T.-W. Chen, C.-S. Chen, C.-F. Shen, S.-Y. Ma, T.-C. Wang, B.-Y. Hsieh, H.-C. Fang, L.-G. Chen, “A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications,” Digest of Technical Papers, 2005 IEEE International Solid-State Circuits Conference (ISSCC 2005), 2005, pp. 128-130
T.-W. Chen, Y.-W. Huang, T.-C. Chen, Y.-H. Chen, C.-Y. Tsai, L.-G. Chen,, “Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos,” Proc. of 2005 International Symposium on Circuits and Systems (ISCAS 2005), 2005, pp. 2931-2934.
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Chen, LG., Lian, CJ., Chen, CY., Chen, TC. (2006). Multimedia IP Development. In: Lin, YL.S. (eds) Essential Issues in SOC Design. Springer, Dordrecht. https://doi.org/10.1007/1-4020-5352-5_3
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DOI: https://doi.org/10.1007/1-4020-5352-5_3
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