Abstract
We present our experience of designing a single-chip multimedia SOC for advanced digital still camera from specification all the way to mass production. The process involves collaboration with camera system designer, IP vendors, EDA vendors, silicon wafer foundry, package & testing houses, and camera maker. We also co-work with academic research groups to develop a JPEG codec IP and memory BIST and SOC testing methodology. In this presentation, we cover the problems encountered, our solutions, and lessons learned. This case study shows the feasibility of expanding semiconductor wafer foundry service to electronics manufacturing service (EMS) providers who in general have very limited IC design capability/experience. We also point out possible directions for future research
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References
C. L. Chen, J. Y. Lin, and Y. L. Lin, “Integration, Verification and Layout of a Complex Multimedia SOC,” DATE-2005, Munich, Germany, March 2005.
C. Christopoulos, A. Skodras, and T. Ebrahimi, “The JPEG2000 Still Image Coding System – An Overview,” IEEE Transactions on Consumer Electronics, 2000
C. J. Lian, Y. W. Huang, H. C. Fang, Y. C. Chang and L. G. Chen, “JPEG, MPEG-4, and H.264 Codec IP Development” DATE-2005, Munich, Germany, March 2005.
C. W. Wu, “SOC Testing Methodology and Practice,” DATE-2005, Munich, Germany, March 2005.
G. K. Wallace and M. Maynard, “The JPEG Still Picture Compression Standard,” Communications of the ACM, 1991.
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© 2006 Springer
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Lin, JY., Chen, CL., Lin, YL. (2006). A SOC Controller for Digital Still Camera. In: Lin, YL.S. (eds) Essential Issues in SOC Design. Springer, Dordrecht. https://doi.org/10.1007/1-4020-5352-5_2
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DOI: https://doi.org/10.1007/1-4020-5352-5_2
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-5351-1
Online ISBN: 978-1-4020-5352-8
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