Abstract
This paper presents a two-step subranging ADC architecture based on interpolation, averaging, offset compensation and pipelining techniques. Application of these techniques results in fast and power-efficient converters with an accuracy between 8b and 12b.
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van der Goes, F. et al. (2007). FAST AND POWER-EFFICIENT CMOS SUBRANGING ADCs. In: Van Roermund, A.H., Casier, H., Steyaert, M. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/1-4020-5186-7_4
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DOI: https://doi.org/10.1007/1-4020-5186-7_4
Publisher Name: Springer, Dordrecht
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