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The Effect of Technology Scaling on Power Dissipation in Analog Circuits

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Analog Circuit Design

Abstract

A general approach for Power Dissipation estimates in Analog circuits as a function of Technology scaling is introduced. It is shown that as technology progresses to smaller dimensions and lower supply voltages, matching dominated circuits are expected to see a reduction in power dissipation whereas noise dominated circuits will see an increase. These finds are applied to ADC architectures like Flash and Pipeline ADC’s and it is shown why Pipeline ADC’s survive better on a high, thick-oxide supply voltage whereas Flash ADC’s benefit from the technology’s thinner oxides. As a result of these calculations an adaptation to the most popular Figure-of-Merit (FOM) for ADC’s

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  1. Broadcom Netherlands - Bunnik, The Netherlands

    Klaas Bult

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  1. Klaas Bult
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  1. Katholieke Universiteit Leuven, Belgium

    Michiel Steyaert

  2. Delft University of Technology, The Netherlands

    Johan H. Huijsing

  3. Eindhoven University of Technology, The Netherlands

    Arthur H.M. van Roermund

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Bult, K. (2006). The Effect of Technology Scaling on Power Dissipation in Analog Circuits. In: Steyaert, M., Huijsing, J., van Roermund, A. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/1-4020-3885-2_13

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  • DOI: https://doi.org/10.1007/1-4020-3885-2_13

  • Publisher Name: Springer, Dordrecht

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  • Online ISBN: 978-1-4020-3885-3

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