In this article we explore systems on programmable chips (SOPCs), that is, the concept of designing and implementing entire digital systems (processor, memory, and I/O, plus special functions and software) on the desktop, using inexpensive programmable chips and freely available tools. Before embarking on an SOPC test design, we first review the characteristics of the two main lines of programmable devices, field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), in the context of their relative advantages for different types of SOPC designs. We then give a brief overview of the primary enabling force for SOPC design, the design framework.
Keywords
- Random Access Memory
- Static Random Access Memory
- Logic Cell
- Hardware Description Language
- Static Random Access Memory Cell
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Hawkins, W.M. (2005). SOPCs: Systems on Programmable Chips. In: Hristu-Varsakelis, D., Levine, W.S. (eds) Handbook of Networked and Embedded Control Systems. Control Engineering. Birkhäuser Boston. https://doi.org/10.1007/0-8176-4404-0_14
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