Identifying Redundant Gate and Wire Replacements

Abstract

In simulation-based verification by an explicit error model, the fundamental problem is that simulations alone, unless exhaustive, cannot identify the everpresent redundant faults. This chapter considers redundant gate and wire replacement faults identification in verification of gate-level designs. Removing redundant faults from a fault list is critical to the quality and speed of verification schemes. We present the exact identification of redundant gate and wire replacement faults, together with efficient approximations. While we rely on the satisfiability formulation of the problem, we propose the means to effectively use any single stuck-at-value redundancy identification in the approximate schemes, with varying detection accuracy. Critical to the latter is the novel application of don’t care approximations that identify many redundant faults and quickly point out those that can be detected by methods for stuck-at value faults. A test generation scheme that uses the errorcorrecting properties of AT, discussed in Chapter 6 is incorporated into the overall verification procedure.