Using Transactional Level Models in a SoC Design Flow

Abstract

Embedded software accounts for more than half of the total development time of a system on a chip (SoC). The complexity of the hardware is becoming so high that the definition of the chip architecture and the verification of the implementation require new techniques. In this chapter we describe our proposed methodology for supporting these new challenges as an extension of the ASIC flow. Our main contribution is the identification and systematic usage in an industrial environment of an abstraction layer that describes SoC architecture to enable three critical activities: early software development, functional verification and architecture analysis. The models are also referred to as Transaction Level Models (TLM) because they rely on the concept of transactions to communicate. Examples of a multimedia platform and of an ARM subsystem highlight practical benefits of our approach.