Clocking Strategies for Networks-on-Chip

Abstract

One of the main problems when designing today’s ASICs, is to distribute a skew-free synchronous clock over the whole chip. A large part of the power is also consumed in the clock-tree, in some cases as much as 50% of the total power consumption of the chip, because the large wires in the clock-tree are switched often. To attack these two problems, several methods have been discussed in the research literature over the years, from the more obvious solution of using asynchronous communication between locally clocked regions (Globally Asynchronous Locally Synchronous - GALS) to more fancy methods like distributing a standing wave on the clock-wires across the whole chip. In this chapter, we go through different clocking methods that has been proposed over the years and are suitable for the NoC scheme as well as presenting a new and clever way of distributing a Quasi-synchronous, i.e., a perfectly synchronous, but not skew-less, clock across an entire NoC-chip.