Mechanisms of Error in Switched-Current Circuits

Summary

This chapter described the main errors responsible for the non-ideal behaviour of SI circuits, namely: finite output-input conductance ratio error, charge injection error, incomplete settling error, mismatch errors and noise. The physical mechanisms behind all of them are explained and a precise modelling of the memory cell is derived. Based on this modelling, the effect of each error on the performance of both single-ended and fully-differential memory cells is analyzed by considering either linear or non-linear errors. As a result of this analysis, closed-form expressions are found for the linear gain error, offset and harmonic distortion.

The knowledge provided by these expressions allow the designer to reduce the errors by properly sizing the cell. Numerical examples, validated by electrical simulations, are given as an illustration. Besides, circuit strategies to reduce SI errors reported up to the present are summarized and compared.

All the analyses have been made at the memory cell level and validated by electrical simulation using HSPICE. In the next chapter we will extend this study to other blocks in the modulator hierarchy such as integrators and resonators. This will allow us to evaluate the impact of each SI error on the performance of bandpass ΣΔ modulators.