Abstract
Memory cells are the fundamental components to all semiconductor memories, and their features predominantly effect the chip-size, operational speed and power dissipation of memory devices. This chapter examines the CMOS-compatible memory cells which are extensively applied or have good potentials to be used in CMOS memories. The examination of the memory cells comprises structural, storage-mechanism, write, read, design and improvement issues. The structural and operational characteristics of a memory cell set the primary parameters for the design of sense amplifier, memory-cell, array, reference and decoder circuits.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
W. P. Noble and W. W. Walker, “Fundamental Limitations on DRAM Storage Capacitors,” IEEE Circuits and Devices Magazine, Vol. 1, No. 1, pp. 45–51, January 1985.
K. W. Kwon et al., “Ta2O5 Capacitors for 1 Gbit DRAM and Beyond,” IEEE International Electron Devices Meeting, Technical Digest, pp. 34.2.1–34.2.4, December 1994.
L. H. Parker and A. F. Tasch, “Ferroelectric Materials for 64 Mb and 256 Mb DRAMs,” IEEE Circuits and Devices Magazine, Vol. 6, No. 1, pp. 17–26, January 1990.
J. C Burfoot, “Ferroelectrics: An Introduction to the Physical Principles,” D. Van Nostrand, 1967.
D. Bursky, “Memory and Logic Structures Are Getting Faster and Denser,” Electronic Design, pp. 40–46, December 1, 1997.
A. Goetzberger and E. Nicollian, “Transient Voltage Breakdown Due to Avalanche in MIS Capacitors,” Applied Physics Letters, Vol. 9, December 1966.
P. Chatterjee et al., “Trench and Compact Structures for DRAMS,” IEEE International Electron Devices Meeting, Technical Digest, pp. 128–131, December 1986.
H. Arima, “A Novel Stacked Capacitor Cell with Dual Cell Plate for 64 Mb DRAMs,” IEEE International Electron Devices Meeting, Technical Digest, pp. 27.2.1–27.2.4, December 1990.
P. C. Fazan and A. Ditali, “Electrical Characterization of Textured Interpoly Capacitors for Advanced Stacked DRAMs,” IEEE International Electron Devices Meeting, Technical Digest, pp. 27.5.1–27.5.4, December 1990.
S. Watanabe et al., “A Novel Circuit Technology with Surrounding Gate Transistors (SGTs) for Ultra High Density DRAMs,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 9, pp. 960–971, September 1995.
K. V. Rao et al., “Trench Capacitor Design Issues in VLSI DRAM Cells,” IEEE International Electron Devices Meeting, Technical Digest, pp. 140–143, December 1986.
W. M. Regitz and J. Karp, “A Three-transistor Cell, 1.024-bit, 500-ns MOS RAM,” International Solid-State Circuit Conference, Digest of Technical Papers, Vol. 13, pp. 42–43, February 1970.
R. G. Middleton, “Designing Electronic Circuits,” Prentice-Hall, pp. 221–226, October 1986.
C. F. Hill, “Noise Margin and Noise Immunity in Logic Circuits,” Microelectron, Vol. 1, pp. 16–21, April 1968.
A. Bryant, W. Hansch and T. Mii, “Characteristics of CMOS Device Isolation for the ULSI Age,” IEEE International Electron Devices Meeting, Technical Digest, pp. 28.1.1–28.1.4, December 1994.
C. E. Chen et al., “Stacked CMOS SRAM Cell,” IEEE Electron Device Letters, Vol. EDL-4, No. 8, pp. 272–274, August 1983.
W. Dunn and T. P. Haraszti, “1-Mbit and 4-Mbit RAMs with Static Polysilicon-Load Memory Cells,” Semi Inc., Technical Report, October 1974.
T. P. Haraszti, “Novel Circuits for High Speed ROMs,” IEEE Journal of Solid State Circuits, Vol. SC-19, No. 2, pp. 180–186, April 1984.
P. R. Gray, D. A. Hodges and R. W. Brodersen, “Analog MOS Integrated Circuits,” IEEE Press, 1980.
T. P. Haraszti, “Circuit-Techniques and Applications of MOS LSI,” (Schaltungs-techniken und Anwendungen von MOS-Grosschaltungen), Semiconductor Seminar, Telefunken, Digest (Kurzfassungen), 1969.
J. T. Koo, “Integrated-Circuit Content-Addressable Memories,” IEEE Journal of Solid-State Circuits, Vol. SC-5, pp. 208–215, October 1970.
R. M. Lea, “Low-Cost High-Speed Associative Memory,” IEEE Journal of Solid-Sttae Circuits, Vol. SC-10, pp. 179–181, June 1975.
S.M.S. Jalaleddine and L. G. Johnson, “Associative IC Memories with Relational Search and Nearest-Match Capabilities, Vol. 27, No. 6, pp. 892–900, June 1992.
T. P. Haraszti, “Flip-Flop Circuits with Tunnel Diodes,” (Billenokorok Alagutdiodakkal), Radiotechnika, Vol. XV, No. 12, pp. 444–447, December 1965.
G. Frazier, et al., “Nanoelectric Circuits Using Resonant Tunelling Transistors and Diodes,” IEEE International Solid-State Circuit Conference, Digest of Technical Papers, pp. 174–175, February 1993.
W. S. Boyle and C. E. Smith, “Charge Coupled Semiconductor Devices,” Bell System Technical Jounral, No. 47(4), pp. 587–593, April 1970.
E. R. Hnatek, “A User’s Handbook of Semiconductor Memories,” John Wiley and Sons, pp. 609–646, 1977.
F. Lai, Y. L. Chuang and S. J. Chen, “A New Design Methodology for Multiport SRAM Cell,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 41, No. 11, pp. 677–685, November 1994.
Rights and permissions
Copyright information
© 2002 Kluwer Academic Publishers
About this chapter
Cite this chapter
(2002). Memory Cells. In: Cmos Memory Circuits. Springer, Boston, MA. https://doi.org/10.1007/0-306-47035-7_2
Download citation
DOI: https://doi.org/10.1007/0-306-47035-7_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-7923-7950-8
Online ISBN: 978-0-306-47035-6
eBook Packages: Springer Book Archive