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Modeling Unknown Values in Test and Verification

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Formal Modeling and Verification of Cyber-Physical Systems

Abstract

With increasing complexities and a component-based design style the handling of unknown values (e. g., at the interface of components) becomes more and more important in electronic design automation (EDA) and production processes. Tools are required that allow an accurate modeling of unknowns in combination with algorithms balancing exactness of representation and efficiency of calculation. In the following, state-ofthe-art approaches are described that enable an efficient and successful handling of unknown values using formal techniques in the areas of Test and Verification.

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References

  1. Roth, J.P.: Diagnosis of automata failures: A calculus and a method. IBM J. Res. Dev. 10(4) (1966) 278–291

    Article  MATH  Google Scholar 

  2. Goel, P.: An implicit enumeration algorithm to generate tests for combinational logic circuits. In: Proc. Fault Tolerant Computing Symposium. (1980) 145–151

    Google Scholar 

  3. Fujiwara, H., Shimono, T.: On the acceleration of test generation algorithms. IEEE Trans. on Computers C-32(12) (1983) 1137 -1144

    Google Scholar 

  4. Larrabee, T.: Test pattern generation using Boolean satisfiability. IEEE Trans. on Computer-Aided Design 11(1) (1992) 4–15

    Article  Google Scholar 

  5. Stephan, P., Brayton, R., Sangiovanni-Vincentelli, A.: Combinational test generation using satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9) (1996) 1167–1176

    Article  Google Scholar 

  6. Czutro, A., Polian, I., Lewis, M., Engelke, P., Reddy, S.M., Becker, B.: Thread- parallel integrated test pattern generator utilizing satisfiability analysis. International Journal of Parallel Programming 38(3–4) (2010) 185–202

    Article  MATH  Google Scholar 

  7. Eggersglüß, S., Drechsler, R.: Atpg based on Boolean satisfiability. In: High Quality Test Pattern Generation and Boolean Satisfiability. Springer (2012) 59–70

    Google Scholar 

  8. Wohl, P., Waicukauski, J., Neuveux, F.: Increasing scan compression by using X-chains. In: Int’l Test Conference (ITC). (2008) 1–10

    Google Scholar 

  9. Ramdas, A., Sinanoglu, O.: Toggle-masking scheme for X-filtering. In: European Test Symposium (ETS). (2012) 1–6

    Google Scholar 

  10. Ahmed, N., Tehranipoor, M.: A novel faster-than-at-speed transition-delay test method considering IR-drop effects. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 28(10) (2009) 1573–1582

    Article  Google Scholar 

  11. Hillebrecht, S., Polian, I., Engelke, P., Becker, B., Keim, M., Cheng, W.T.: Extraction, simulation and test generation for interconnect open defects based on enhanced aggressor-victim model. In: Int’l Test Conference (ITC). (2008) 1–10

    Google Scholar 

  12. Muth, P.: A nine-valued circuit model for test generation. IEEE Trans. on Computers C-25(6) (1976) 630–636

    Google Scholar 

  13. Flores, P., Neto, H., Marques Silva, J.: An exact solution to the minimum size test pattern problem. In: IEEE Int’l Conf. on Computer Design (ICCD). (1998) 510–515

    Google Scholar 

  14. Jain, A., Boppana, V., Mukherjee, R., Jain, J., Fujita, M., Hsiao, M.: Testing, verification, and diagnosis in the presence of unknowns. In: IEEE VLSI Test Symposium (VTS). (2000) 263–268

    Google Scholar 

  15. Carter, J., Rosen, B., Smith, G., Pitchumani, V.: Restricted symbolic evaluation is fast and useful. In: IEEE/ACM Int’l Conf. on Computer Aided Design (ICCAD). (1989) 38 -41

    Google Scholar 

  16. Kundu, S., Nair, I., Huisman, L., Iyengar, V.: Symbolic implication in test generation. In: Proc. Conference on European Design Automation. (1991) 492–496

    Google Scholar 

  17. Touba, N.: X-canceling MISR : An X-tolerant methodology for compacting output responses with unknowns using a MISR. In: Int’l Test Conference (ITC). (2007) 1–10

    Google Scholar 

  18. Tang, Y., Wunderlich, H., Engelke, P., Polian, I., Becker, B., Schloffel, J., Hapke, F., Wittke, M.: X-masking during logic BIST and its impact on defect coverage. IEEE Trans. on Very Large Scale Integration (VLSI) Systems 14(2) (2006) 193–202

    Article  Google Scholar 

  19. Elm, M., Kochte, M.A., Wunderlich, H.J.: On determining the real output Xs by SAT-based reasoning. In: IEEE Asian Test Symposium (ATS). (2010) 39–44

    Google Scholar 

  20. Chou, H.Z., Chang, K.H., Kuo, S.Y.: Accurately handle don’t-care conditions in high-level designs and application for reducing initialized registers. IEEE Trans. on Computer-Aided Design 29(4) (2010) 646–651

    Article  Google Scholar 

  21. Wilson, C., Dill, D., Bryant, R.: Symbolic simulation with approximate values. In Hunt, W., Johnson, S., eds.: Int’l Conf. on Formal Methods in Computer Aided Design (FMCAD). Vol. 1954 of LNCS. Springer (2000) 507–522

    Google Scholar 

  22. Kochte, M.A., Elm, M., Wunderlich, H.J.: Accurate X-propagation for test applications by SAT-based reasoning. IEEE Trans. on Computer-Aided Design 31(12) (2012) 1908–1919

    Article  Google Scholar 

  23. Hillebrecht, S., Kochte, M.A., Wunderlich, H.J., Becker, B.: Exact stuck-at fault classification in presence of unknowns. In: European Test Symposium (ETS). (2012) 1–6

    Google Scholar 

  24. Erb, D., Kochte, M.A., Sauer, M., Hillebrecht, S., Schubert, T., Wunderlich, H.J., Becker, B.: Exact logic and fault simulation in presence of unknowns. ACM Trans. on Design Automation of Electronic Systems (TODAES) 19(3) (2014)

    Google Scholar 

  25. Biere, A., Heule, M., van Maaren, H., Walsh, T., eds. Frontiers in Artificial Intelligence and Applications 185. In: Handbook of Satisfiability. IOS Press (2009)

    Google Scholar 

  26. Zhang, L., Malik, S.: Conflict driven learning in a quantified Boolean satisfiability solver. In: IEEE/ACM Int’l Conf. on Computer Aided Design (ICCAD). (2002) 442–449

    Google Scholar 

  27. Biere, A.: Resolve and expand. In: Int’l Conf. on Theory and Applications of Satisfiability Testing (SAT). Vol. 3542 of LNCS, Springer (2005) 59–70

    Google Scholar 

  28. Giunchiglia, E., Marin, P., Narizzano, M.: sQueezeBF: An effective preprocessor for QBFs based on equivalence reasoning. In: Int’l Conf. on Theory and Applications of Satisfiability Testing (SAT). Vol. 6175 of LNCS. Springer (2010) 85–98

    Google Scholar 

  29. Bloem, R., Konighofer, R., Seidl, M.: SAT-based synthesis methods for safety specs. In: Int’l Conf. on Verification, Model Checking, and Abstract Interpretation (VMCAI). Vol. 8318 of LNCS, Springer (2014) 1–20

    Google Scholar 

  30. Bloem, R., Egly, U., Klampfl, P., Konighofer, R., Lonsing, F.: SAT-based methods for circuit synthesis. In: Int’l Conf. on Formal Methods in Computer Aided Design (FMCAD), IEEE (2014) 31–34

    Google Scholar 

  31. Scholl, C., Becker, B.: Checking equivalence for partial implementations. In: ACM/IEEE Design Automation Conference (DAC), ACM Press (2001) 238–243

    Google Scholar 

  32. Jo, S., Matsumoto, T., Fujita, M.: SAT-based automatic rectification and debugging of combinational circuits with LUT insertions. In: IEEE Asian Test Symposium (ATS), Niigata, Japan, IEEE Computer Society (2012) 19–24

    Google Scholar 

  33. Jo, S., Gharehbaghi, A.M., Matsumoto, T., Fujita, M.: Debugging processors with advanced features by reprogramming LUTs on FPGA. In: Int’l Conf. on Field-Programmable Technology (FPT), Kyoto, Japan, IEEE (2013) 50–57

    Google Scholar 

  34. Smith, A., Veneris, A.G., Ali, M.F., Viglas, A.: Fault diagnosis and logic debugging using boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10) (2005) 1606–1621

    Article  Google Scholar 

  35. Sülflow, A., Fey, G., Drechsler, R.: Using QBF to increase accuracy of SAT-based debugging. In: Int’l Symposium on Circuits and Systems (ISCAS), Paris, France, IEEE (2010) 641–644

    Google Scholar 

  36. Gitina, K., Reimer, S., Sauer, M., Wimmer, R., Scholl, C., Becker, B.: Equivalence checking of partial designs using dependency quantified Boolean formulae. In: IEEE Int’l Conf. on Computer Design (ICCD), Asheville, NC, USA, IEEE Computer Society (2013) 396–403

    Google Scholar 

  37. Clarke, E.M., Emerson, E.A., Sistla, A.P.: Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications. ACM Trans. on Programming Languages and Systems 8(2) (1986) 244–263

    Article  MATH  Google Scholar 

  38. Nopper, T., Scholl, C.: Symbolic model checking for incomplete designs with flexible modeling of unknowns. IEEE Trans. on Computers 62(6) (2013) 1234–1254

    Article  MathSciNet  Google Scholar 

  39. Miller, C., Kupferschmid, S., Lewis, M.D.T., Becker, B.: Encoding techniques, craig interpolants and bounded model checking for incomplete designs. In: Int’l Conf. on Theory and Applications of Satisfiability Testing (SAT). Vol. 6175 of LNCS, Springer (2010) 194–208

    Google Scholar 

  40. Miller, C., Scholl, C., Becker, B.: Proving QBF-hardness in bounded model checking for incomplete designs. In: Int’l Workshop on Microprocessor Test and Verification (MTV), IEEE Computer Society (2013)

    Google Scholar 

  41. Sauer, M., Reimer, S., Polian, I., Schubert, T., Becker, B.: Provably Optimal Test Cube Generation Using Quantified Boolean Formula Solving. In: Asia and South Pacific Design Automation Conference (ASPDAC). (2013) 533–539

    Google Scholar 

  42. Reimer, S., Sauer, M., Schubert, T., Becker, B.: Using maxbmc for pareto-optimal circuit initialization. In: Int’l Conf. on Design, Automation & Test in Europe (DATE), IEEE (2014) 1–6

    Google Scholar 

  43. Cook, S.A.: The complexity of theorem-proving procedures. In: Annual ACM Symposium on Theory of Computing (STOC), ACM (1971) 151–158

    Google Scholar 

  44. Stockmeyer, L.J., Meyer, A.R.: Word problems requiring exponential time (preliminary report). In: Annual ACM Symposium on Theory of Computing (STOC), New York, NY , USA, ACM (1973) 1–9

    Google Scholar 

  45. Gitina, K., Wimmer, R., Reimer, S., Sauer, M., Scholl, C., Becker, B.: Solving DQBF through quantifier elimination. In: Int’l Conf. on Design, Automation & Test in Europe (DATE), Grenoble, France, IEEE (2015)

    Google Scholar 

  46. Fröhlich, A., Kovasznai, G., Biere, A., Veith, H.: iDQ: Instantiation-based DQBF solving. In: Intl. Workshop on Pragmatics of SAT (POS), Vienna, Austria (2014)

    Google Scholar 

  47. Tseitin, G.S.: On the complexity of derivation in propositional calculus. Studies in Constructive Mathematics and Mathematical Logic Part 2 (1970) 115–125

    Google Scholar 

  48. Turpin, M.: The dangers of living with an X (bugs hidden in your Verilog). In: Boston Synopsys Users Group Meeting. (2003) 1–34

    Google Scholar 

  49. Ulrich, E.G., Baker, T.: The concurrent simulation of nearly identical digital networks. In: Papers on Twenty-five years of electronic design automation. 25 years of DAC (1988) 318–323

    Google Scholar 

  50. Waicukauski, J., Eichelberger, E., Forlenza, D., Lindbloom, E., McCarthy, T.: Fault simulation for structured VLSI. VLSI Systems Design 6(12) (1985) 20–32

    Google Scholar 

  51. Antreich, K., Schulz, M.: Accelerated fault simulation and fault grading in combinational circuits. IEEE Trans. on Computer-Aided Design 6(5) (1987) 704–712

    Article  Google Scholar 

  52. Lee, H., Ha, D.: An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagation. In: Int’l Test Conference (ITC). (1991) 946–955

    Google Scholar 

  53. Rudnick, E., Patel, J., Pomeranz, I.: On potential fault detection in sequential circuits. In: Int’l Test Conference (ITC). (1996) 142–149

    Google Scholar 

  54. Schubert, T., Lewis, M., Becker, B.: Antom—solver description. SAT Race (2010)

    Google Scholar 

  55. Hillebrecht, S., Kochte, M.A., Erb, D., Wunderlich, H.J., Becker, B.: Accurate QBF-based test pattern generation in presence of unknown values. In: Int’l Conf. on Design, Automation & Test in Europe (DATE). (2013) 436–441

    Google Scholar 

  56. Pnueli, A., Rosner, R.: Distributed reactive systems are hard to synthesize. In: Annual Symposium on Foundations of Computer Science, IEEE Computer Society (1990) 746–757

    Google Scholar 

  57. Miller, C., Nopper, T., Scholl, C.: Symbolic CTL model checking for incomplete designs by selecting property-specific subsets of local component assumptions. In: Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen” (MBMV), Universitätsbibliothek Berlin, Germany (2009) 87–96

    Google Scholar 

  58. Nopper, T., Scholl, C.: Approximate symbolic model checking for incomplete designs. In: Int’l Conf. on Formal Methods in Computer Aided Design (FMCAD). Vol. 3312 of LNCS, Springer (2004) 290–305

    Google Scholar 

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Becker, B., Sauer, M., Scholl, C., Wimmer, R. (2015). Modeling Unknown Values in Test and Verification. In: Drechsler, R., Kühne, U. (eds) Formal Modeling and Verification of Cyber-Physical Systems. Springer Vieweg, Wiesbaden. https://doi.org/10.1007/978-3-658-09994-7_5

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  • DOI: https://doi.org/10.1007/978-3-658-09994-7_5

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