Abstract
Here, three new low power single bit full adders using 9 and 10 transistor have been presented. The proposed adders have the advantage of low power consumption with small area requirements due less number of transistors. Low power objective has been achieved at circuit level by designing the adder with optimized XOR gates and multiplexer approach. Direct path between supply voltage and ground have been minimized in these designs. The circuits have been simulated in 0.18μm CMOS technology using SPICE. The first adder shows power dissipation of 23.8595pW with maximum output delay of 67.5566fs at supply voltage of 1.8V. The second adder shows power dissipation of 43.1258pW with maximum output delay of 58.9935fs. Third adder shows power dissipation of 33.5163pW with delay of 62.065fs. Further, simulations have been carried out with different supply voltage [1.8 - 3.3] V. Power consumption of proposed full adders have been compared with earlier reported circuits and proposed circuit’s shows better results.
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Kumar, M., Pandey, S., Arya, S.K. (2011). Design of CMOS Energy Efficient Single Bit Full Adders. In: Mantri, A., Nandi, S., Kumar, G., Kumar, S. (eds) High Performance Architecture and Grid Computing. HPAGC 2011. Communications in Computer and Information Science, vol 169. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22577-2_23
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DOI: https://doi.org/10.1007/978-3-642-22577-2_23
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