Abstract
Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems, swapping in and out HW tasks. To coordinate the on-demand task execution, we propose and implement a run time system manager for scheduling software (SW) tasks on available processor(s) and hardware (HW) tasks on any number of reconfigurable regions of a partially reconfigurable FPGA. Fed with the initial partitioning of the application into tasks, the corresponding task graph, and the available task mappings, the RTSM considers the runtime status of each task and region, e.g. busy, idle, scheduled for reconfiguration/execution, etc., to execute tasks. Our RTSM supports task reuse and configuration prefetching to minimize reconfigurations, task movement among regions to efficiently manage the FPGA area, and RR reservation for future reconfiguration and execution. We validate its correctness using our RTSM to execute an image processing application on a ZedBoard platform. We also evaluate its features within a simulation framework, and find that despite the technology limitations, our approach can give promising results in terms of quality of scheduling.
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References
Steiger, C., Walder, H., Platzne, M.: Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of RealTime Tasks. IEEE Transactions on Computers 53(11) (2004)
Marconi, T., Lu, Y., Bertels, K., Gaydadjiev, G.: 3D compaction: a novel blocking-aware algorithm for online hardware task scheduling and placement on 2d partially reconfigurable devices. In: Sirisuk, P., Morgan, F., El-Ghazawi, T., Amano, H. (eds.) ARC 2010. LNCS, vol. 5992, pp. 194–206. Springer, Heidelberg (2010)
Lu, Y., Marconi, T., Bertels, K.L.M. Gaydadjiev, G.N.: A communication aware online task scheduling algorithm for FPGA-based partially reconfigurable systems. In: Proc. of the IEEE Symposium on Field-Programmable Custom Computing Machines (2010)
Bazargan, K., Kastner, R., Sarrafzadeh, M.: Fast Template Placement for Reconfigurable Computing Systems. IEEE Design and Test of Computers 17(1), 68–83 (2000)
Compton, K., Li, Z., Cooley, J., Knol, S., Hauck, S.: Configuration Relocation and Defragmentation for Run-Time Reconfigurable Systems. IEEE Trans. on VLSI, 10(3) (2002)
Burns, J., Donlin, A., Hogg, J., Singh, S., de Wit, M.: A dynamic reconfiguration run-time system. In: Proc. of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (1997)
Durelli, G., Pilato, C., Cazzaniga, A., Sciuto, D., Santambrogio, M.D.: Automatic run-time manager generation for reconfigurable MPSoC architectures. In: 7th International Workshop on Reconfigurable Communication-centric Systems-onChip (ReCoSoC) (2012)
Lysaght, P., Blodget, B., Mason, J., Young, J., Bridgford, B.: Invited paper: enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of xilinx FPGAs. In: Proc. FPL 2006, pp. 1–6 (2006)
Bauer, L., Grudnitsky, A., Shafique, M., Henkel, J.: PATS: a performance aware task scheduler for runtime reconfigurable processors. In: Proc. of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (2012)
Morales-Villanueva, A., Gordon-Ross, A.: On-chip context save and restore of hardware tasks on partially reconfigurable FPGAs. In: Proc. of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (2013)
Göhringer, D., Hübner, M., Nguepi Zeutebouo, E., Becker, J.: Operating System for Runtime Reconfigurable Multiprocessor Systems. Int. J. Reconfig. Comp. 2011 (2011)
Göhringer, D., Werner, S., Hübner, M., Becker, J.: RAMPSoCVM: runtime support and hardware virtualization for a runtime adaptive MPSoC. In: Proc. FPL 2011, pp. 181–184 (2011)
Conger, C., Gordon-Ross, A., George, A.D.: Design framework for partial run-time FPGA reconfiguration. In: ERSA 2008, pp. 122–128 (2008)
Li, Z., Hauck, S.: Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. In: FPGA 2002, pp. 187–195 (2002)
Vipin, K., Fahmy, S.A.: Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration. In: Choy, O.C., Cheung, R.C., Athanas, P., Sano, K. (eds.) ARC 2012. LNCS, vol. 7199, pp. 13–25. Springer, Heidelberg (2012)
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Charitopoulos, G., Koidis, I., Papadimitriou, K., Pnevmatikatos, D. (2015). Hardware Task Scheduling for Partially Reconfigurable FPGAs. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_45
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DOI: https://doi.org/10.1007/978-3-319-16214-0_45
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