Overview
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Table of contents (13 chapters)
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Front Matter
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Models of Sequential Systems
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Back Matter
Keywords
About this book
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
Authors and Affiliations
Bibliographic Information
Book Title: Logic Synthesis and Verification Algorithms
Authors: Gary D. Hachtel, Fabio Somenzi
DOI: https://doi.org/10.1007/b117060
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 1996
Hardcover ISBN: 978-0-7923-9746-5Published: 30 June 1996
Softcover ISBN: 978-1-4757-7036-0Published: 18 March 2013
eBook ISBN: 978-0-306-47592-4Published: 17 December 2005
Edition Number: 1
Number of Pages: XXXII, 564
Topics: Circuits and Systems, Logics and Meanings of Programs, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design, Discrete Mathematics in Computer Science, Artificial Intelligence