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Comparative analysis of CMOS adders circuits based on 10 transistors

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Abstract

Development of digital signal processing devices has led to appearance of a series of CMOS circuit designs of arithmetic and logic blocks with a small number of transistors. In this paper we suggest a classification of full single-bit CMOS adders, circuits of which consist of 10 transistors. The comparison of main characteristics of adders has been carried out based on the results of circuit simulation for 0.18-micron MOS technology and the most promising implementations have been marked out.

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Authors and Affiliations

  1. St. Petersburg State Polytechnical University, St. Petersburg, Russia

    M. M. Pilipko & D. V. Morozov

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  1. M. M. Pilipko
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  2. D. V. Morozov
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Correspondence to M. M. Pilipko.

Additional information

Original Russian Text © M.M. Pilipko, D.V. Morozov, 2014, published in Izv. Vyssh. Uchebn. Zaved., Radioelektron., 2014, Vol. 57, No. 9, pp. 42–54.

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Pilipko, M.M., Morozov, D.V. Comparative analysis of CMOS adders circuits based on 10 transistors. Radioelectron.Commun.Syst. 57, 418–427 (2014). https://doi.org/10.3103/S0735272714090040

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  • DOI: https://doi.org/10.3103/S0735272714090040

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