Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

Abstract

The Network-on-Chip (NoC) is an emerging communication technique for System-on-Chip (SoC) communications. The NoC uses multiple processors, usually targeted for embedded applications and other applications [3, 13]. Performance of the bus is degraded by the increasing number of processing elements and transaction oriented model [13]. This has attracted much attention for applying wireless network protocols as CDMA, TDMA, and dTDMA in SoC. The TDMA systems use a fixed number of timeslots. This protocol wastes bandwidth when some timeslots are allocated but not used. The dynamic TDMA (dTDMA) bus arbiter dynamically grows and shrinks the number of timeslots to match the number of active transmitters [14]. In this paper, we present a design of area-efficient switch for inter-layer communications in 3-D NoC. The arbitration logic in the switch is based on a programmable priority encoder. A 640-bit message with uniform random destination data pattern was injected per IP per machine clock cycle. We have obtained the maximum clock frequency of 2.09 GHz for 96(4 × 8 × 3) IP cores connected in a mesh topology. The presented architecture demonstrates their superior functionality in terms of speed, latency, area, and power consumption as compared with the existing implementation [14]. The maximum power consumption of the proposed area-efficient programmable arbiter is 0.625 mW. The design is synthesized using 180nm TSMC Technology.