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Design of adiabatic two’s complement multiplier-accumulator based on CTGAL

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Abstract

We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic (CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two’s complement multiplier-accumulator (MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor (CMOS) logic.

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Authors and Affiliations

  1. Institute of Circuits and Systems, Ningbo University, Ningbo, 315211, China

    Peng-jun Wang & Jian Xu

  2. College of Information Engineering, Zhejiang University of Technology, Hangzhou, 310014, China

    Shi-yan Ying

Authors
  1. Peng-jun Wang
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  2. Jian Xu
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  3. Shi-yan Ying
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Correspondence to Peng-jun Wang.

Additional information

Project supported by the National Natural Science Foundation of China (No. 60776022), the Science and Technology Fund of Zhejiang Province (No. 2008C21166), the Key Scientific Research Fund of the Department of Education of Zhejiang Province (No. 20061666), the Professor Fund (No. JSL2007001), the Scientific Research Fund (No. XK0610030) and the K. C. Wong Magna Fund in Ningbo University, China

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Wang, Pj., Xu, J. & Ying, Sy. Design of adiabatic two’s complement multiplier-accumulator based on CTGAL. J. Zhejiang Univ. Sci. A 10, 172–178 (2009). https://doi.org/10.1631/jzus.A0820013

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  • DOI: https://doi.org/10.1631/jzus.A0820013

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