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New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency

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Abstract

This paper suggests three techniques on non-scan DFT of sequential circuits. The proposed techniques guarantee 100% fault efficiency by using combinational ATPG tool. In all the techniques, an additional circuit called CRIS is proposed to reach unreachable states on the state register of a machine. The second and third techniques use an additional hardware DL to uniquely identify a state appearing in a state register. The design of DL is universal. Test length and hardware overhead outperform the similar approaches.

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References

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Authors and Affiliations

  1. Department of Comp. Sc. and Engg., Jadavpur University, Kolkata, 700 032, India

    Debesh Kumar Das

  2. Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5, Takayama-Cho, Ikoma, Nara, 630-0101, Japan

    Satoshi Ohtake & Hideo Fujiwara

Authors
  1. Debesh Kumar Das
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  2. Satoshi Ohtake
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  3. Hideo Fujiwara
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Das, D.K., Ohtake, S. & Fujiwara, H. New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. Journal of Electronic Testing 20, 315–323 (2004). https://doi.org/10.1023/B:JETT.0000029464.22206.0c

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  • DOI: https://doi.org/10.1023/B:JETT.0000029464.22206.0c

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