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A Hardware Architecture for the LZW Compression and Decompression Algorithms Based on Parallel Dictionaries

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Abstract

In this paper, a parallel dictionary based LZW algorithm called PDLZW algorithm and its hardware architecture for compression and decompression processors are proposed. In this architecture, instead of using a unique fixed-word-width dictionary a hierarchical variable-word-width dictionary set containing several dictionaries of small address space and increasing word widths is used for both compression and decompression algorithms. The results show that the new architecture not only can be easily implemented in VLSI technology because of its high regularity but also has faster compression and decompression rate since it no longer needs to search the dictionary recursively as the conventional implementations do.

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Authors and Affiliations

  1. Department of Electronic Engineering, National Taiwan University of Science and Technology, 43, Keelung Road Section 4, Taipei, Taiwan

    Ming-Bo Lin

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  1. Ming-Bo Lin
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Lin, MB. A Hardware Architecture for the LZW Compression and Decompression Algorithms Based on Parallel Dictionaries. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 26, 369–381 (2000). https://doi.org/10.1023/A:1026559601791

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  • DOI: https://doi.org/10.1023/A:1026559601791

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