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An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

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Abstract

The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

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Authors and Affiliations

  1. Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, 721302, West Bengal, India

    Baishik Biswas, Rohan Mukherjee, Priyabrata Saha & Indrajit Chakrabarti

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  1. Baishik Biswas
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  2. Rohan Mukherjee
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  3. Priyabrata Saha
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  4. Indrajit Chakrabarti
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Correspondence to Baishik Biswas.

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Biswas, B., Mukherjee, R., Saha, P. et al. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm. J. Inst. Eng. India Ser. B 97, 303–309 (2016). https://doi.org/10.1007/s40031-014-0177-x

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  • DOI: https://doi.org/10.1007/s40031-014-0177-x

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