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Hybrid redundancy approach to increase the reliability of FPGA based speed controller core for high speed train

  • Published:
Journal of Electronics (China)

Abstract

With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger’s safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a new effective method which is based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy (HDDR) method, the original controller is quadruplicated and correct values are voted through the comparator and error detection unit. We have analyzed the proposed system with Reliability, Availability, Mean time to failure and Security (RAMS) theory in order to evaluate the effectiveness of proposed scheme. Theoretical analysis shows that the Mean Time To Failure (MTTF) of the proposed system is 2.5 times better than the traditional Triple Modular Redundancy (TMR). Furthermore, the fault injection experimental results reveal that the capability of tolerating Single Event Upsets (SEUs) in the proposed method increases up to 7.5 times with respect to a regular speed controller.

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References

  1. H. Dong, B. Ning, B. Cai, and Zh. Hou. Automatic train control system development and simulation for high-speed railways. IEEE Circuits and Systems Magazine, 10(2012)2, 6–8.

    Article  Google Scholar 

  2. L. Zhou and Zh. Shen. Progress in high speed train technology around the world. Journal of Modern Transportation, 19(2011)1, 1–6.

    Article  Google Scholar 

  3. M. Geunhong. A study on a safety activity on safety critical related software in train control system. Annual Conference & Exhibition of the Korean Society of Automotive Engineers, Daejeon, South Korea, Vol. 2, 1077–1083.

  4. M. S. Kim, M. K. Kim, and J. W. Lee. Reliability analysis for train control system by hardware redundancy architecture in fault tolerances. Journal of International Council on Electrical Engineering, 1 (2011)2, 140–144.

    Article  Google Scholar 

  5. L. Schiano, C. Metra, and D. Marino. Self checking design, implementation, and measurement of a controller for track-side railway systems. IEEE Transactions on Instrumentation and Measurement, 52 (2003)6, 1722–1728.

    Article  Google Scholar 

  6. E. Q. Daddario. Automatic train control in rail rapid transit. Office of Technology Assessment, Washington, D. C., USA, 1976.

    Google Scholar 

  7. J. R. Andina, M. J. Moure, and M. D. Valdes. Features, design tools, and application domains of FPGAs. IEEE Transactions on Industrial Electronics, 54(2007)4, 1810–1823.

    Article  Google Scholar 

  8. J. Huang, M. B. Tahoori, and F. Lombardi. Fault tolerance of switch blocks and switch block arrays in FPGA. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(2005)7, 794–807.

    Article  Google Scholar 

  9. E. Monmasson and M. N. Cirstea. FPGA design methodology for industrial control systems-a review. IEEE Transactions on Industrial Electronics, 54(2007) 4, 1824–1842.

    Article  Google Scholar 

  10. C. T. Yen, W. D. Weng, and Y. T. Lin. FPGA realization of a neural network based nonlinear channel equalizer. IEEE Transactions on Industrial Electronics, 51(2004)2, 472–479.

    Article  Google Scholar 

  11. H. Asadi and M. B. Tahoori. Analytical techniques for soft error rate modeling and mitigation of FPGA based designs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(2007)12, 1320–1331.

    Article  Google Scholar 

  12. H. G. Miranda, L. Sterpone, M. Violante, M. A. Aguirre and M. G. Rizo. Coping with the obsolescence of safety or mission critical embedded systems using FPGAs. IEEE Transactions on Industrial Electronics, 58(2011)3, 814–821.

    Article  Google Scholar 

  13. S. Liu, G. Sorrenti, P. Reviriego, F. Casini, J. A. Maestro, M. Alderighi and H. Mecha. Comparison of the susceptibility to soft errors of SRAM based FPGA error correction codes implementations. IEEE Transactions on Nuclear Science, 59(2012)3, 619–624.

    Article  Google Scholar 

  14. F. Abate, L. Sterpone, C. A. Lisboa, L. Carro and M. Violante. New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors. IEEE Transactions on Nuclear Science, 56(2009)4, 1992–2000.

    Article  Google Scholar 

  15. E. Mortlock. Technical Memorandum of ATC: Concept of System. California High Speed Train Project, PB Press, 2010.

    Google Scholar 

  16. M. Matsumoto, S. Kitamura, and M. Sato. High assurance technologies for autonomous decentralized train control system. IEEE International Symposium on High Assurance Systems Engineering, Boco Raton, FL, USA, October 22–24, 2001, 220–227.

  17. S. G. Wei, C. B. Gen, G. Chen, W. Jian, and W. J. Jing. Research on reliability evaluation of high speed railway train control system based on fault injection. International Conference on Environmental Science and Information Application Technology (ESIAT), Wuhan, China, July 17–18, 2010, 288–293.

  18. B. Burstrom, G. Ericsson, and V. U. Kjellsson. Verification of life cycle cost and reliability for the Swedish high speed train X2000. Annual Reliability and Maintainability Symposium, Anaheim, CA, USA, January 24–27, 1994, 166–171.

  19. O. Akbari, K. Mohammadi, and R. Omidi Gosheblagh. A speed controller system based on FPGA for high speed train. 2nd International Conference on Recent Advances in Railway Engineering (ICRARE), Iran University of Science and Technology, Tehran, Iran, April 30–May 1, 2013, 1–7.

    Google Scholar 

  20. R. Omidi Gosheblagh and K. Mohammadi. Dynamic partial based Single Event Upset (SEU) injection platform on FPGA. International Journal of Computer Applications, 76(2013)3, 19–24.

    Article  Google Scholar 

  21. S. Yasunobu and T. Hasegawa. Evaluation of an automatic container crane operation system based on predictive fuzzy control. Control Theory and Advanced Technology, 2(1986)3, 419–432.

    Google Scholar 

  22. M. Matsumoto. The revolution of train control system in Japan. East Japan Railway Autonomous Decentralized Systems (ISADS), Tokyo, Japan, April 4–8, 2005, 599–606.

  23. Y. Ichinomiya. Improving the robustness of a soft core processor against SEUs by using TMR and partial reconfiguration. IEEE International Symposiumon Field-Programmable Custom Computing Machines (FCCM), Charlotte, NC, USA, May 2–4, 2010, 47–54.

  24. W. Wei, Y. J. Zhang, and M. Jie. The research of FPGA reliability based on redundancy methods. International Conference on Computer Science and Network Technology, Harbin, China, December 24–26, 2011, 1608–1611.

  25. E. Stott, P. Sedcole, and P. Cheung. Fault tolerance and reliability in field programmable gate arrays. IET Computer Digital Technology, 4(2010)3, 196–210.

    Article  Google Scholar 

  26. Y. Hayashi, N. Homma, T. Sugawara, T. Mizuki, T. Aoki, and H. Sone. Non-invasive trigger-free fault injection method based on intentional electromagnetic interference. In Non-Invasive Attack Testing Workshop (NIAT), Nara, Japan, September 25–27, 2011, 15–19.

  27. I. Koren and C. M. Krishna. Fault Tolerant Systems. Morgan-Kaufman Publishers, San Francisco, CA, USA, 2007.

    MATH  Google Scholar 

  28. R. Noji, S. Fujie, Y. Yoshikawa, H. Ichihara, and T. Inoue. Reliability and performance analysis of FPGA based fault tolerant system. 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Chicago, IL, USA, 7–9 Oct. 2009, 245–253.

  29. S. Pontarelli, M. Ottavi, and V. Vankamamidi. Analysis and evaluations of reliability of reconfigurable FPGAs. Journal of Electronic Testing, 24(2008)1, 105–116.

    Article  Google Scholar 

  30. D. K. Pradhan and J. A. Abraham. Fault Tolerant Computing: Theory and Techniques. Prentice-Hall, Englewood Cliffs, NJ, USA, 1986.

    Google Scholar 

  31. L. Antoni, R. Leveugle, and B. Feher. Using run-time reconfiguration for fault injection applications. IEEE Transactions on Instrumentation and Measurement, 52(2003)1, 1468–1473.

    Article  Google Scholar 

  32. L. O. Celia, G. V. Mario, P. G. Marta, and E. Luis. Autonomous fault emulation: a new FPGA based acceleration system for hardness evaluation. IEEE Transactions on Nuclear Science, 54(2007)1, 252–261.

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electrical Engineering, Iran University of Science and Technology (IUST), Narmak, Tehran, 16846-13114, Iran

    Omid Akbari Galashi, Karim Mohammadi & Reza Omidi Gosheblagh

Authors
  1. Omid Akbari Galashi
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  2. Karim Mohammadi
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  3. Reza Omidi Gosheblagh
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Corresponding author

Correspondence to Omid Akbari Galashi.

Additional information

Communication author: Omid Akbari Galashi, born in 1989, male, MS Student.

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Galashi, O.A., Mohammadi, K. & Gosheblagh, R.O. Hybrid redundancy approach to increase the reliability of FPGA based speed controller core for high speed train. J. Electron.(China) 31, 256–266 (2014). https://doi.org/10.1007/s11767-014-4011-z

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  • DOI: https://doi.org/10.1007/s11767-014-4011-z

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