Skip to main content
Log in

Architecture Considerations for Multi-Format Programmable Video Processors

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but a programmable processor is important for applications that support multiple coding standards, proprietary functions, or future changes to application requirements. Programmable video processor architectures achieve best performance through the use of parallelism at the data (SIMD), instruction (VLIW), and multiprocessor level, and optimally sized ALU, multiplier, and load/store datapaths. Because low-cost memory architectures are not optimized for the random access patterns of video processing, the performance of video processors is often limited by memory bandwidth rather than processing resources. Careful data organization alleviates memory bandwidth limitations. When choosing a video processor it is important to consider many factors, particularly performance, cost, power consumption, programmability, and peripheral support.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. “VW2000 MPEG-2 Video Encoder Product Brief,” Vweb Corporation, 2000.

  2. “CS7050 H.264 Decoder,” Amphion Semiconductor Ltd., 2004.

  3. I. Richardson, “H.264 and MPEG-4 Video Compression,” Wiley, 2003.

    Google Scholar 

  4. S. Srinivasan, “An Introduction to VC-1,” 2005.

  5. G. Ezer, “High-Performance Multicore Video Decoder Technology Preview,” Tensilica Inc., 2005.

  6. “TMS320C6414, TMS320C6415, TMS320C6416, Fixed-Point Digital Signal Processors,” Texas Instruments Incorporated, 2005.

  7. “StarCore SC140 Application Development Tutorial,” Freescale Semiconductor, Inc., 2004.

  8. “Pixels to Packets: Enabling Multi-Format High Definition Video,” Equator Technologies, 2004.

  9. “TMS320DM644x Processors—Video Benchmarks,” Texas Instruments Incorporated, 2005.

  10. “Product Brief: CT3600 Family of Multiprocessor DSPs,” Cradle Technologies Inc., 2005.

  11. “Product Brief T1P2000 Video Processor,” Telairity Semiconducor, 2005.

  12. “Processors for Consumer Video Applications,” Berkeley Design Technologies, Inc., 2005.

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Jonah Probell.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Probell, J. Architecture Considerations for Multi-Format Programmable Video Processors. J Sign Process Syst Sign Image 50, 33–39 (2008). https://doi.org/10.1007/s11265-007-0116-z

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-007-0116-z

Keywords

Navigation