Skip to main content
SpringerLink
Log in

A novel laminated gate to improve the ON-state resistance of LDMOS transistors

  • Published:
Journal of Computational Electronics Aims and scope Submit manuscript

Abstract

A novel power transistor structure, namely the laminated gate laterally diffused metal–oxide–semiconductor (LG-LDMOS) structure, is proposed herein. The proposed structure has an extra lateral gate located in the middle of the channel region in addition to the fin-shaped gate. This technique provides additional inversion channels. In this way, the channel resistance is reduced and also the power losses decrease due to improved gate control on the channel. The ON-state resistance of the proposed structure is improved by 52 % compared with a LDMOS structure with fin-shaped gate (Fin-LDMOS).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

References

  1. Antognetti, P.: Power Integrated Circuits: Physics, Design and Applications. McGraw-Hill, New York (1986)

    Google Scholar 

  2. Wang, H., Xu, H.P.E., Ng, W.T., Fukumot, K., Abe, K., Ishikawa, A., Furukawa, Y., Imai, H., Naito, T., Sato, N., Sakai, K., Tamura, S., Takasuka, K.: A novel orthogonal gate EDMOS transistor with improved dv/dt capability and figure of merit (FOM). IEEE Electron Device Lett. 29, 1386–1388 (2008)

    Article  Google Scholar 

  3. Fujishima, N., Sugi, A., Kajiwara, S., Matsubara, K., Nagayasu, Y., Salama, A.T.: A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact. IEEE Trans. Electron Devices 49, 1462–1468 (2002)

    Article  Google Scholar 

  4. Moens, P., Bauwens, F., Baele, J., Vershinin, K., De Backer, E.: The first integrated power transistor breaking the silicon limit. Int. Electron Devices Meet. 27, 1–4 (2006)

    Google Scholar 

  5. Appels, J.A., Vaes, H.M.J.: High voltage thin layer devices (RESURFdevices). IEDM Tech. Dig. 25, 238–241 (1979)

    Google Scholar 

  6. Fujihira, T.: Theory of semiconductor superjunction devices. Jpn. J. Appl. Phys. 36, 6254–6262 (1997)

    Article  Google Scholar 

  7. Erlbacher, T.: Lateral Power Transistors in Integrated Circuits. Springer, Cham (2014)

    Book  Google Scholar 

  8. Device simulator ATLAS, Silvaco International, \(\langle \) http://www.silvaco.com \(\rangle \), (2012)

  9. Mehrad, M., Orouji, A.A.: New trench gate power MOSFET with high breakdown voltage and reduced on-resistance using a SiGe zone in drift region. Curr. Appl. Phys. 12, 1340–1344 (2012)

    Article  Google Scholar 

  10. Orouji, A.A., Pak, A.: A novel technique on the electric field control at LDMOSs to improve the breakdown voltage. Mater. Sci. Semicond. Process. 34, 230–235 (2015)

    Article  Google Scholar 

  11. Disney, D., Chan, W., Lam, R., Blattner, R., Ma, S., Seng, W., Chen,J. W., Cornell, M., Williams, R.: 60V lateral trench MOSFET in \(0.35\, \upmu \text{m}\) technology. In: Proceedings 20th ISPSD & IC’s,24–27 (2008)

  12. Atlas user’s manual: device simulation software, Silvaco International, (2012)

  13. Moens, P., Bauwens, F., Desoete, B., Baele, J., Vershinin, K., Ziad,H., Shankara Narayanan, E.M., Tack, M.: Record-low on-resistance for \(0.35\, \upmu \text{ m }\)  based integrated XtreMOS\(^{{\rm TM}}\)transistors. In: Proceedings 19th ISPSD & IC’s, 57–60 (2007)

Download references

Author information

Authors and Affiliations

  1. Electrical and Computer Engineering Department, Semnan University, Semnan, Iran

    Amin Pak & Ali A. Orouji

Authors
  1. Amin Pak
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ali A. Orouji
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ali A. Orouji.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Pak, A., Orouji, A.A. A novel laminated gate to improve the ON-state resistance of LDMOS transistors. J Comput Electron 15, 1071–1076 (2016). https://doi.org/10.1007/s10825-016-0867-5

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10825-016-0867-5

Keywords

Search

Navigation