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Investigation of trigate JLT with dual-k sidewall spacers for enhanced analog/RF FOMs

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Abstract

This paper shows the potential benefits of using the trigate junctionless transistor (JLT) with dual-k sidewall spacers to enhance analog/radio-frequency (RF) performance at 20-nm gate length. Simulation study shows that the source-side-only dual-k spacer (dual-kS) JLT can improve all analog/RF figures of merit (FOMs) compared with the conventional JLT structure. The dual-kS JLT shows improvement in intrinsic voltage gain (\(A_{V0}\)) by \(\sim \)44.58 %, unity-gain cutoff frequency (\(f_\mathrm{T}\)) by \(\sim \)7.67 %, and maximum oscillation frequency (\(f_\mathrm{MAX}\)) by \(\sim \)6.4 % at drain current \((I_\mathrm{ds}) = 10\,\upmu \hbox {A}/\upmu \hbox {m}\) compared with the conventional JLT structure. To justify the improvement in all analog/RF FOMs, it is also found that the dual-kS structure shows high electron velocity near the source region because of the presence of an additional electric field peak near the source region, resulting in increased electron transport efficiency and hence improved transconductance (\(g_\mathrm{m}\)). Furthermore, the dual-kS JLT shows a reduction in the electric field value near the drain end, thereby improving short-channel effects.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, NIT Kurukshetra, Kurukshetra, Haryana, India

    Gaurav Saini & Sudhanshu Choudhary

  2. School of VLSI Design and Embedded Systems, NIT Kurukshetra, Kurukshetra, Haryana, India

    Gaurav Saini & Sudhanshu Choudhary

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  1. Gaurav Saini
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  2. Sudhanshu Choudhary
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Correspondence to Gaurav Saini.

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Saini, G., Choudhary, S. Investigation of trigate JLT with dual-k sidewall spacers for enhanced analog/RF FOMs. J Comput Electron 15, 865–873 (2016). https://doi.org/10.1007/s10825-016-0866-6

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  • DOI: https://doi.org/10.1007/s10825-016-0866-6

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