A low-jitter third-order self-biased PLL with adaptive fast-locking scheme for SerDes interfaces

Abstract

This paper presents a 3rd-order self-biased phase-locked loop (PLL) with adaptive fast-locking scheme for serialize/deserialize (SerDes) interfaces. In order to obtain short and almost equal power-up latency in a wide range of reference frequencies, a fast-locking circuit block including 2 switched-capacitor frequency-to-voltage (F–V) converters and an adaptive discharger is proposed to speed up the power-up process. Additionally, the current in the charge pump (CP) of the traditional self-biased PLL tends to be influenced by the kick-back noise from the voltage-controlled oscillator (VCO). In order to reduce the jitter resulted from the VCO kick-back noise, an additional bias generator is inserted between the original bias generator and the VCO to isolate the bias signals for the CP and the VCO. The simulated clock jitter under 100-mV, 1-MHz supply noise is 27 ps at an output frequency of 2 GHz, which is much lower than that of the traditional counterpart. The presented PLL is integrated in a SerDes interface chip fabricated in a 0.25-μm standard CMOS technology. Measurement results show that the presented PLL achieves a power-up latency of 4–6.5 μs in the output frequency range of 200 MHz–2 GHz, and the peak-to-peak data jitter of the SerDes chip is 110 ps at a data rate of 2.5 Gbps. The presented PLL consumes 217 mW under a 2.5-V power supply, and the block area is 350 × 600 μm².