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A compact CMOS current-mode analog multi-functions circuit

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Abstract

A new CMOS current-mode analog multifunction circuit is proposed. The proposed circuit is capable of performing multiplication, squaring, division, and different types of controllable gain amplifiers. The design is based on translinear principle using MOSFETs operating in subthreshold region. The proposed design is compact and operates from ±0.6 V DC power supply. The functionality of the design was confirmed using Tanner Tspice with 0.18 µm CMOS technology. Simulation results show that the −3 dB frequency is around 1.5 MHz, linearity error of 0.63 %, THD of 0.08 % when configured as an amplifier, and the maximum power consumption is 1.16 µW.

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References

  1. Mahmoudi, A., Khoei, A. & Hadidi, K.H. (2007). A novel current-mode micropower four-quadrant cmos analog multiplier/divider. In IEEE Conference on Electron Devices and Solid-State Circuits 2007, Taiwan.

  2. Kaewdang, K., Fongsamut, C. & Surakampontorn, W. (2003). A wide-band current-mode OTA-based analog multiplier-divider. In Proceedings of the 2003 International Symposium on Circuits and Systems, 2003 (ISCAS ‘03) (vol. 1, pp. I-349–I-352, pp. 25–28).

  3. Graupner, A. & Schüffny, R. (1999). An ultra-low-power switched-current 2-quadrant multiplier. In 2nd Electronic Circuits and Systems Conference (ECS’99), Bratislava, Slovakia.

  4. Salama, M. K., & Ahmed, A. M. (2003). Low-voltage low-power CMOS RF four-quadrant multiplier. AEU - International Journal of Electronics and Communications, 57(1), 74–78.

    Article  Google Scholar 

  5. Popa, Cosmin. (2014). Improved accuracy current-mode multiplier circuits with applications in analog signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(2), 443–447.

    Article  Google Scholar 

  6. Naderi, Ali, Khoei, Abdollah, Hadidi, Khayrollah, & Ghasemzadeh, Hadi. (2009). A new high speed and low power four-quadrant CMOS analog multiplier in current mode. AEU - International Journal of Electronics and Communications, 63(9), 769–775.

    Article  Google Scholar 

  7. Psychalinos, C., & Laoudias, C. (2013). Low-voltage reduced complexity cells for MOS translinear loops. Circuits, Systems, and Signal Processing, 32(5), 2445–2456.

    Article  MathSciNet  Google Scholar 

  8. Keleş, S., & Kuntman, H. (2011). Four quadrant FGMOS analog multiplier. Turkish Journal of Electrical Engineering & Computer Sciences, 19(2), 291–301.

    Google Scholar 

  9. Liu, Weihsing, & Liu, Shen-Iuan. (2010). Design of a CMOS low-power and low-voltage four-quadrant analog multiplier. Analog Integrated Circuits and Signal Processing, 63(2), 307–312.

    Article  Google Scholar 

  10. Panigrahi, A., & Paul, P. K. (2013). A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion. Analog Integrated Circuits and Signal Processing, 75(2), 237–243.

    Article  Google Scholar 

  11. Liu, Shen-Iuan, & Chen, Po-Ki. (1996). Low-voltage CMOS subthreshold four-quadrant tripler. Analog Integrated Circuits and Signal Processing, 11(3), 303–307.

    Article  Google Scholar 

  12. Chang, C.-C., & Liu, S.-I. (1998). Weak inversion four-quadrant multiplier and two-quadrant divider. Electronics Letters, 34(22), 2079–2080.

    Article  Google Scholar 

  13. Lin, K.-J., Cheng, C.-J., Chiu, S.-F., & Su, H.-C. (2012). CMOS current-mode implementation of fractional-power functions. Circuits, Systems, and Signal Processing, 31(1), 61–75.

    Article  MathSciNet  MATH  Google Scholar 

  14. Pesavento, A., Koch, C., A wide linear range four quadrant multiplier in subthreshold CMOS,”In ISCAS ‘99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems 1999 (ISCAS ‘99). (vol. 2, pp. 240–243).

  15. Gravati, M., Valle, M., Ferri, G., Guerrini, N., Reyes, L. (2005) A novel current-mode very low power analog CMOS four quadrant multiplier. In Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005), Grenoble, France (pp. 495–498).

  16. Tanno, K., Sugahara, Y., Tamura, H., (2011). High-linear four-quadrant multiplier based on MOS weak-inversion region translinear principle with adaptive bias technique, In IEEE Region 10 Conference 2011. TENCON 2011 (pp. 680–684).

  17. Al-Absi, M. A., Hussain, A., & Abuelmaatti, M. T. (2013). A low voltage and low power analog computational circuit. Journal of circuits, system and signal processing, 32(1), 321–331.

    Article  Google Scholar 

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Acknowledgments

The authors would like to thank KFUPM for supporting this research.

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Correspondence to Munir A. Al-Absi.

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Al-Suhaibani, E.S., Al-Absi, M.A. A compact CMOS current-mode analog multi-functions circuit. Analog Integr Circ Sig Process 84, 471–477 (2015). https://doi.org/10.1007/s10470-015-0554-7

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  • DOI: https://doi.org/10.1007/s10470-015-0554-7

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