Abstract
This paper presents a 2:1 low power switched-capacitor DC–DC converter designed in \(180\) nm Standard CMOS technology. The converter operates from \(1.8\) V input and delivers a \(0.8\) V power supply with \(50\) mA load current. Simplicity and power efficiency improvement is the main goal of this design. The achieved efficiency of the converter is more than \(80\,\%\). Also, high power efficiency, high current delivery, small size, low output voltage ripples are some main properties of the proposed DC–DC converters. The converter occupies about an area of \(1\) mm\(^2\). Besides, switching frequency of the switched-capacitor DC-DC converter has been increased to reduce output voltage ripples. Maximum output voltage ripple is about \(21\) mV. Power saving in gate driver stage is the method used in this design to improve the power efficiency. Also, a little changes applied in non-overlapping clock signal generator to gain a better power efficiency. During the design procedure, the main power loss sources have been explained and their solutions have been presented.
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The authors would like to thank Mr. Saeed Ghiasi, Mrs. Jafarnejad and Mrs. Sheikholeslami for their helpful supports and feedbacks.
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Rikhtegar Ghiasi, R., Sahafi, A., Sobhi Geshlaghi, J. et al. A 2:1 switched-capacitor DC–DC converter for low power circuits. Analog Integr Circ Sig Process 84, 215–222 (2015). https://doi.org/10.1007/s10470-015-0551-x
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DOI: https://doi.org/10.1007/s10470-015-0551-x