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“Skip–Swap” method instead of “Skip–Fill” method in background calibration of pipelined ADCs

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Abstract

This paper presents a new background calibration technique employing an extra slow but accurate ADC for correcting the linear and nonlinear gain errors in pipelined ADCs. In comparison to the well-known skip–fill method, the proposed skip–swap algorithm enables the calibration of the pipelined ADC with low power consumption and fast convergence, while usable in Nyquist frequencies with low SNDR degradation. The simulation results for a behaviorally modeled 12-bit 200MS/s 1.5bit/stage pipelined ADC show the improvement of DNL and INL from 88.2 and 209 LSB to 0.89 and 1.06 LSB, respectively. The ADC achieves a SNDR of 72.5 dB after calibration.

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References

  1. Chiu, Y., Tsang, C. W., Nikolic, B., & Gray, P. R. (2004). Least mean square adaptive digital background calibration of pipelined analog-to-digital converters. IEEE Transactions on Circuits and Systems, 51(1), 38–46.

    Article  Google Scholar 

  2. Moon, U. K., & Song, B. S. (1997). Background digital calibration techniques for pipelined ADCs. IEEE Transactions on Circuits and Systems, 44(2), 102–109.

    Article  Google Scholar 

  3. Sahoo, B., & Razavi, B. (2009). A 12-bit 200-MHz CMOS ADC. IEEE Journal of Solid-State Circuits, 44(9), 2366–2380.

    Article  Google Scholar 

  4. Verma, A., & Razavi, B. (2009). A 10-bit 500-MS/s 55-mW CMOS ADC. IEEE Journal of Solid-State Circuits, 44(11), 3039–3050.

    Article  Google Scholar 

  5. Ingino, J. M., & Wooley, B. A. (1998). A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter. IEEE Journal of Solid-State Circuits, 33, 1920–1931.

    Article  Google Scholar 

  6. Wang, H., Wang, X., Hurst, P. J., & Lewis, S. H. (2009). Nested digital background calibration of a 12-bit pipelined ADC without an input SHA. IEEE Journal of Solid-State Circuits, 44(10), 2780–2789.

    Article  Google Scholar 

  7. Lee, C. C., & Flynn, M. P. (2011). A SAR-assisted two-stage pipeline ADC. IEEE Journal of Solid-State Circuits, 46(4), 859–862.

    Article  Google Scholar 

  8. Abbaszadeh, A., & Sadeghipour, K. D. (2009). A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCs. In Proceedings of the IEEE SiPS (pp. 202–207).

  9. Grace, C. R., Hurst, P. J., & Lewis, S. H. (2005). A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration. IEEE Journal of Solid-State Circuits, 40, 1038–1046.

    Article  Google Scholar 

  10. Ning, Q., Jiantou, G., Kai, Z., Bo, Y., Zhongli, L., & Fang, Y. (2011). A 14-bit wide temperature range differential SAR ADC with an on-chip multi-segment BGR. Journal of Semiconductors, 32(8), 085003.

    Article  Google Scholar 

  11. Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2012). A 0.5 V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS. IEEE Journal of Solid-State Circuits, 47(4), 1022–1030.

    Article  Google Scholar 

  12. Jalili, A., Sayedi, S. M., Wikner, J. J., & Nezhad, A. Z. (2011). A nonlinearity error calibration technique for pipelined ADCs. VLSI Journal, 44, 229–241.

    Article  Google Scholar 

  13. Yuan, J., Fung, S. W., Chan, K. Y., & Xu, R. (2012). An interpolation-based calibration architecture for pipeline ADC with nonlinear error. IEEE Transactions on Instrumentation and Measurement, 61(1), 17–25.

    Article  Google Scholar 

  14. Sonkusale, S. R., Spiegel, J. V., & Nagaraj, K. (2001). Background digital error correction technique for pipelined analog-digital converters. In IEEE ISCAS (Vol. 1, pp. 408–411).

  15. Tsang, C. W. (2008). Digitally calibrated analog-to-digital converters in deep sub-micron CMOS. Thesis, University of California at Berkeley.

  16. Wang, X., Hurst, P. J., & Lewis, S. H. (2004). A 12-bit 20-M samples/s pipelined analog-to-digital converter with nested digital background calibration. IEEE Journal of Solid-State Circuits, 39, 1799–1808.

    Article  Google Scholar 

  17. Murmann, B., & Boser, B. E. (2004). Digitally assisted pipeline ADCs: Theory and implementation. Berlin: Springer.

    Google Scholar 

  18. Chen, D., et al. (2005). An adaptive, truly background calibration method for high speed pipeline ADC design. In IEEE International Symposium on Circuits and Systems, ISCAS 2005 (pp. 6190–6193).

  19. Panigada, A., & Galton, I. (2006). Digital background correction of harmonic distortion in pipelined ADCs. IEEE Transactions on Circuits and Systems I: Regular Papers, 53, 1885–1895.

    Article  Google Scholar 

  20. Massolini, R. G., et al. (2006). A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC. IEEE Transactions on Circuits and Systems II: Express Briefs, 53, 389–393.

    Article  Google Scholar 

  21. Moosazadeh, T., & Yavari, M. (2010). A novel digital calibration technique for pipelined ADCs. IEICE Electronics Express, 7, 1741–1746.

    Article  Google Scholar 

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Correspondence to Meysam Mohammadi Khanghah.

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Mohammadi Khanghah, M., Alipour Asl, A., Najafi Aghdam, E. et al. “Skip–Swap” method instead of “Skip–Fill” method in background calibration of pipelined ADCs. Analog Integr Circ Sig Process 84, 127–135 (2015). https://doi.org/10.1007/s10470-015-0550-y

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  • DOI: https://doi.org/10.1007/s10470-015-0550-y

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