Abstract
Comparators are essential components of ADCs, and largely affect their overall performance. Among the performance metrics of the comparator, the noise is the most difficult to estimate and simulate, specially for circuits that present a time-varying behavior such as clocked comparators. In this work we present a framework to size and optimize comparators which uses periodic steady-state (PSS) and periodic noise (PNOISE) analyses, commonly employed for RF circuits, together with an optimization kernel based on evolutionary algorithms. We present a case study comparator design, taking into account noise, power and delay. The results show that the proposed framework minimizes these parameters and achieves systematic convergence to consistent Pareto fronts in a short timespan (approximately 27 mins). Furthermore, the accuracy of the PSS/PNOISE noise estimation method is validated through comparison to extensive transient noise simulations, showing a difference standard deviation of 3.47 % between the two methods.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Rabuske, T., Rabuske, F., Fernandes, J., & Rodrigues, C. An 8-bit 0.35-V 5.04-fJ/conversion-step SAR ADC with background self-calibration of comparator offset. IEEE Transactions on VLSI Systems, accepted
Craninckx, J., & Van der Plas, G. (2007). A 65fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90nm digital CMOS. In: IEEE international solid-state circuits conference (ISSCC) (pp. 246–247)
Harpe, P., Cantatore, E., & van Roermund, A. (2013). A 2.2/2.7 fJ/conversion-step 10/12b 40 kS/s SAR ADC with data-driven noise reduction. In: IEEE international solid-state circuits conference (ISSCC) (pp. 270–271)
Nuzzo, P., De Bernardinis, F., Terreni, P., & Van der Plas, G. (2008). Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(6), 1441–1454.
Kim, J., Leibowitz, B., Ren, J., & Madden, C. (2009). Simulation and analysis of random decision errors in clocked comparators. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(8), 1844–1857.
Kundert, K. (1999). Introduction to RF simulation and its application. IEEE Journal of Solid-State Circuits, 34(9), 1298–1319.
Hajimiri, A., & Lee, T. (1998). A general theory of phase noise in electrical oscillators. IEEE Journal of Solid-State Circuits, 33(2), 179–194.
Kim, J., Leibowitz, B., & Jeeradit, M. (2008). Impulse sensitivity function analysis of periodic circuits. In: IEEE/ACM international conference on computer-aided design (ICCAD) (pp. 386–391)
Deb, K., Pratap, A., Agarwal, S., & Meyarivan, T. (2002). A fast and elitist multiobjective genetic algorithm: Nsga-ii. IEEE Transactions on Evolutionary Computation, 6(2), 182–197.
Scholten, A., Tiemeijer, L., van Langevelde, R., Havens, R., Zegers-van Duijnhoven, A., & Venezia, V. (2003). Noise modeling for RF CMOS circuit simulation. IEEE Transactions on Electron Devices, 50(3), 618–632.
Acknowledgments
This work has been supported by FCT, Fundação para a Ciência e a Tecnologia (Portugal), under projects PEst-OE/EEI/LA0021/2013 and DISRUPTIVE (EXCL/EEI-ELC/0261/2012); and CNPq, Conselho Nacional de Desenvolvimento Científico e Tecnológico (Brazil) Ph.D. Grant 201887/2011-8.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Rabuske, T., Fernandes, J. Noise-aware simulation-based sizing and optimization of clocked comparators. Analog Integr Circ Sig Process 81, 723–728 (2014). https://doi.org/10.1007/s10470-014-0428-4
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-014-0428-4