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CMOS design of a four-quadrant multiplier based on a novel squarer circuit

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Abstract

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a −3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.

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Authors and Affiliations

  1. Microelectronics Research Laboratory, Urmia University, Urmia, Iran

    Naser Beyraghi, Abdollah Khoei & Khayrollah Hadidi

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  1. Naser Beyraghi
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  2. Abdollah Khoei
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  3. Khayrollah Hadidi
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Correspondence to Naser Beyraghi.

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Beyraghi, N., Khoei, A. & Hadidi, K. CMOS design of a four-quadrant multiplier based on a novel squarer circuit. Analog Integr Circ Sig Process 80, 473–481 (2014). https://doi.org/10.1007/s10470-014-0367-0

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  • DOI: https://doi.org/10.1007/s10470-014-0367-0

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