Abstract
A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of −80 dBc/Hz at 10 kHz offset, −95 dBc/Hz at 100 kHz offset, and −120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.
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References
European Broadcasting Union, ETSI ES 201 980-2005,Digital Radio Mondiale(DRM); System Specification[S]Switzerland: Joint Technical Committee (JTC) Broadcast of the European Broadcasting Union (EBU), 2005.
European Broadcasting Union, ETSI EN 300 401-2006,Digital Audio Broadcasting (DAB) to Mobile, Portable and Fixed Receivers[S]. Switzerland: Joint Technical Committee (JTC) Broadcast of the European Broadcasting Union (EBU), 2006.
Luff, G. F., Tuncer, S., Troop, N. M. et al. (2005). A compact triple-band Eureka-147 RF tuner with an FM receiver, Vol. 1 In IEEE International Solid-State Circuits Conference, February. 2005, pp. 434-608.
Jianzheng, Z., & Zhigong, W. (2008). Frequency planning of RFfront-end for DRM receivers. Chinese High Technology Letter, 18, 480–487.
Zhang, M., Haider, M. R., Islam, S. K., et al. (2010). A low-voltage low-power programmable fractional PLL in 0.18-μm CMOS process. Analog Integrated Circuits and Signal Processing, 65(1), 33–42.
Saeedi, S., & Atarodi, M. (2010). Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation[J]. Analog Integrated Circuits and Signal Processing, 64(2), 103–113.
Ren, S., Emmert, J., & Siferd, R. (2011). Design and performance of a robust 180 nm CMOS standalone VCO and the integrated PLL[J]. Analog Integrated Circuits and Signal Processing, 68(3), 285–298.
Ippolito C M, Italia A, Palmisano G. (2010). A 1.7 mW dual-band CMOS frequency synthesizer for low data-rate sub-GHz applications[C]//ESSCIRC, In Proceedings of the. IEEE, 2010. P 142-145.
Wan S, Chen Z, Yu Z, et al. (2009). An embedded 14-bit 800MS/s DAC for direct digital frequency synthesizer in 0.18 μm CMOS[C]//, In Applied Superconductivity and Electromagnetic Devices, 2009. ASEMD 2009. International Conference on. IEEE, 2009. P 97-100.
Lin HC, (2005). Low phase noise design techniques for phase locked loop based integrated RF frequency synthesizers. p 29-36.
Kitsunezuka, M., Kodama, H., Oshima, N., et al. (2012). A 30–2.4 GHz CMOS receiver with integrated RF filter and dynamic-range-scalable energy detector for cognitive radio systems. Solid-State Circuits, IEEE Journal of, 2012, 47(5), 1084–1093.
Bouhamame, M., Coco, L. L., Amiot, S., et al. (2012). A 60 dB harmonic rejection mixer for digital terrestrial TV tuner. Circuits and Systems I: Regular Papers, IEEE Transactions on, 59(3), 471–478.
Tan, J. Y. J., Kian, A. N., & Yong, P. X. (2008). An integrated low power one-pin crystal oscillator 2008. IEEE Asia Pacific Conference on. IEEE, Circuits and Systems, (APCCAS 2008). IEEE.
Hussein, K., Karim, M., & Hegazi, E. (2012). An all-analog method to enhance amplitude stability in Pierce crystal oscillators. Circuits and Systems I: Regular Papers, IEEE Transactions on, (2012), 59(3), 463–470.
Zeng X., et al. (2010). A fast start-up, low-power differential crystal oscillator for DRM/DAB receiver. 12th IEEE International Conference on. IEEE Communication Technology (ICCT), 2010 IEEE.
Moreira, L. C. et al. (2009). A Pulse Generator UWB-Ultra Wide Band using PFD Phase Frequency Detector in 180 nm CMOS Technology. Microwave and Optoelectronics Conference (IMOC), 2009 SBMO/IEEE MTT-S International. IEEE.
Razavi, B. (2001). Design of Analog CMOS Integrated Circuits. USA: McGraw Hill.
Acknowledgment
This work is partially supported by the National Natural Science Foundation of China (No. 61106024, No. 61201176), Special Fund of Jiangsu Province for the Transformation of Scientific and Technological Achievements (No. BA2011009), and the Specialized Research Fund for the Doctoral Program of Higher Education, China (No. 20090092120012). The authors wish to thank Keping Wang, Wei Li and Li Zhang for technical instructions. The authors also gratefully acknowledge the helpful comments and suggestions of the reviewers, which have improved the presentation.
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Wang, J., Wang, Z., Xu, J. et al. A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems. Analog Integr Circ Sig Process 80, 293–304 (2014). https://doi.org/10.1007/s10470-014-0341-x
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DOI: https://doi.org/10.1007/s10470-014-0341-x